Integration methods to fabricate internal spacers for nanowire devices

Patent metadata

Field	Value
Publication number	US-9893167-B2
Application number	US-201415118838-A
Country	US
Kind code	B2
Filing date	Mar 24, 2014
Priority date	Mar 24, 2014
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing photo-definable spacer material in dimples etched adjacent to the channel region. Photo-definable material remains in the dimples by altering the etch characteristics of material outside of the dimples and selectively removing altered photo-definable material outside of the dimples.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires;
a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls;
an external spacer on a portion of the gate sidewalls above the nanowire stack, wherein the external spacer is opaque;
a pair of source/drain regions on opposite sides of the channel region; and
an internal spacer on a portion of the gate sidewalls between two adjacent nanowires, internal to the nanowire stack, the internal spacer comprising a photo-definable dielectric material.

2. The semiconductor device of claim 1 , wherein the photo-definable dielectric material is cross-linked.

3. The semiconductor device of claim 2 , wherein the photo-definable dielectric material comprises a silsesquioxane (SSQ) base resist and a photo destructive base.

4. The semiconductor device of claim 3 , wherein the photo destructive base is paired with a photoacid generator (PAG).

5. The semiconductor device of claim 3 , wherein the photo destructive base comprises the conjugate base of an organic acid as the anion and a photoactive cation.

6. The semiconductor device of claim 5 , wherein the activity of the photo destructive base is enhanced by adding additional functional groups to the anion such as amine or alcohol.

7. The semiconductor device of claim 1 , wherein the external spacer has a first thickness normal to the surface of the gate sidewall, wherein the internal spacers have a second thickness normal to the gate sidewall, and wherein the second thickness is equal to the first thickness.

8. A method for forming internal spacers of a semiconductor device, comprising:
providing a structure having:
a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires separated by sacrificial material;
a gate structure defining a channel region of the device;

a pair of external spacers on opposite sides of the gate structure, wherein the pair of external spacers is opaque; and
a pair of source/drain regions on opposite sides of the channel region;

forming an opening by removing the gate structure and the sacrificial material directly below the gate structure;
forming a dimple by removing the sacrificial material between the nanowires in the source/drain region and below the pair of external spacers;
filling the opening and the dimple with a photo-definable dielectric material;
modifying the photo-definable dielectric material in the opening; and
removing the modified photo-definable dielectric material in the opening with a wet developer such that a portion of the photo-definable dielectric material remains in the dimple.

9. The method of claim 8 , further comprising forming a mask above the external spacers.

10. The method of claim 9 , wherein the mask comprises an optically opaque material.

11. The method of claim 10 , wherein the optically opaque material is a material selected from the group consisting of a nitride and a carbide.

12. The method of claim 9 , wherein the mask comprises an optically reflective material.

13. The method of claim 12 , wherein the optically reflective material is titanium nitride.

14. The method of claim 8 , wherein modifying the photo-definable dielectric material is a chemical modification performed by exposure to electromagnetic radiation with off axis illumination.

15. The method of claim 14 , wherein the electromagnetic radiation is visible light.

16. The method of claim 14 , wherein the electromagnetic radiation is ultraviolet light.

17. The method of claim 8 , wherein modifying the photo-definable dielectric material is a chemical modification performed by exposure to particle beam with off axis illumination.

18. The method of claim 17 , wherein the particle beam is an ion beam.

19. The method of claim 17 , wherein the particle beam is an electron beam.

20. The method of claim 8 , wherein the dimples are etched in alignment with the external spacers.

21. The method of claim 8 , wherein filling the dimples with spacer material comprises a wet spin-on of photo-definable spacer material on the exposed nanowire surfaces.

22. The method of claim 21 , further comprising transforming the photo-definable spacer material within the channel region, wherein transforming the spacer material comprises altering the etch selectivity of the spacer material by changing its molecular polarity.

23. The method of claim 8 , further comprising curing the photo definable dielectric material at a temperature greater than 250° C.

24. The method of claim 23 , wherein curing the photo-definable dielectric material comprises ultraviolet (UV) light exposure.

25. The method of claim 23 , wherein curing the photo-definable dielectric material comprises ion beam exposure.

26. A method for forming internal spacers of a semiconductor device, comprising:
providing a structure having:
nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires separated by sacrificial material;
a gate structure defining a channel region of the device;

a pair of external spacers on opposite sides of the gate structure; and
a pair of source/drain regions on opposite sides of the channel region;

forming a mask above the external spacers;
forming an opening by removing the gate structure and the sacrificial material directly below the gate structure;
forming a dimple by removing the sacrificial material between the nanowires in the source/drain region and below the pair of external spacers;
filling the opening and the dimple with a photo-definable dielectric material;
modifying the photo-definable dielectric material in the opening; and
removing the modified photo-definable dielectric material in the opening with a wet developer such that a portion of the photo-definable dielectric material remains in the dimple.

27. The method of claim 26 , wherein the mask comprises an optically opaque material.

28. The method of claim 27 , wherein, the optically opaque material is a material selected from the group consisting of a nitride and a carbide.

29. The method of claim 26 , wherein the mask comprises an optically reflective material.

30. The method of claim 29 , wherein the optically reflective material is titanium nitride.

Assignees

• Intel Corp

Inventors

• Kim Seiyon
• Simon Daniel A
• Kuhn Kelin J
• Ward Curtis W

Classifications

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H01L29/66545

  Electricity · mapped topic

• H01L21/764

  Electricity · mapped topic

• H01L29/66553 Primary

  Electricity · mapped topic