Asymmetric formation approach for a floating gate of a split gate flash memory structure
US-2015372121-A1 · Dec 24, 2015 · US
US9893160B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9893160-B2 |
| Application number | US-201314081277-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 15, 2013 |
| Priority date | Oct 19, 2010 |
| Publication date | Feb 13, 2018 |
| Grant date | Feb 13, 2018 |
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A method of fabricating a semiconductor device includes contacting water with a silicon oxide layer. The method further includes diffusing an ozone-containing gas through water to treat the silicon oxide layer. The method further includes forming a dielectric layer over the treated silicon oxide layer.
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What is claimed is: 1. A method of fabricating a semiconductor device, the method comprising: contacting water with a silicon oxide layer; diffusing an ozone-containing gas through water to treat the silicon oxide layer, wherein treating the silicon oxide layer comprises increasing a thickness of the silicon oxide layer; and forming a dielectric layer over the treated silicon oxide layer. 2. The method of claim 1 , wherein the silicon oxide layer has a thickness less than about 1 nanometer (nm). 3. The method of claim 1 , wherein the silicon oxide layer has a thickness ranging from about 0.3 nm to about 1 nm. 4. The method of claim 1 , wherein increasing the thickness of the silicon oxide layer comprises increasing the thickness by less than or equal to 10 Angstroms (Å). 5. The method of claim 1 , wherein forming the dielectric layer comprises forming a layer comprising at least one of one of AlO, HfO, ZrO, ZrO 2 , ZrSiO, YO, Y 2 O 3 , LaO, La 2 O 5 , GdO, Gd 2 O 5 , TiO, TiO 2 , TiSiO, TaO, Ta 2 O 5 , TaSiO, HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfSiO, HfTaO, HfSiO, SrTiO, ZrSiON, HfZrTiO, HfZrSiON, HfZrLaO, or HfZrAlO. 6. The method of claim 1 , further comprises forming a gate electrode layer over the dielectric layer, the gate electrode layer comprising at least one of silicon, polysilicon, TiN, TaN, TaC, TaSiN, WN, TiAl, W, Al, or Cu. 7. The method of claim 1 , further comprising cleaning a substrate using a vapor, wherein the silicon oxide layer is over the substrate, and the cleaning is performed prior to contacting water with the silicon oxide layer. 8. The method of claim 7 , wherein cleaning the substrate comprises using a vapor comprising fluorine. 9. The method of claim 7 , wherein cleaning the substrate comprises cleaning the substrate at a temperature less than about 100 degrees Celsius and at a pressure between atmospheric pressure and about 300 torr. 10. The method of claim 7 , wherein cleaning the substrate comprises cleaning the substrate at a temperature less than about 100 degrees Celsius and at a pressure between 1 millitorr (mtorr) and about 10 torr, and then baking the substrate at a temperature from about 50 degrees Celsius to about 200 degrees Celsius. 11. The method of claim 8 , wherein cleaning the substrate comprises using the vapor further comprising an alcohol. 12. The method of claim 1 , wherein forming the dielectric layer comprises forming a high dielectric constant (high-k) dielectric layer. 13. The method of claim 1 , further comprising nitridizing a portion of the treated silicon oxide layer. 14. The method of claim 13 , wherein nitridizing the portion of the treated silicon oxide layer comprises forming a silicon oxynitride layer at an interface of the dielectric layer and the treated silicon oxide layer. 15. A method of fabricating a semiconductor device, the method comprising: contacting water with a silicon oxide layer; diffusing an ozone-containing gas through water to treat the silicon oxide layer, wherein treating the silicon oxide layer comprises increasing a thickness of the silicon oxide layer; forming a dielectric layer over the treated silicon oxide layer; and nitridizing at least a portion of the silicon oxide layer to form a silicon oxynitride layer. 16. The method of claim 15 , further comprising cleaning a substrate using a vapor, wherein the silicon oxide layer is over the substrate, and the cleaning is performed prior to contracting water with the silicon oxide layer. 17. The method of claim 16 , wherein cleaning the substrate comprises using a vapor comprising fluorine and at least one of isopropyl alcohol (IPA), methanol, or ammonia. 18. The method of claim 15 , wherein cleaning the substrate comprises using the vapor further comprising hydrofluoric acid and IPA, wherein a weight percentage of hydrofluoric acid in the vapor ranges from about 10 weight % to about 80 weight %. 19. The method of claim 15 , wherein forming the dielectric layer comprises forming a high dielectric constant (high-k) dielectric layer. 20. The method of claim 15 , wherein forming the dielectric layer comprises forming a layer comprising at least one of one of AlO, HfO, ZrO, ZrO 2 , ZrSiO, YO, Y 2 O 3 , LaO, La 2 O 5 , GdO, Gd 2 O 5 , TiO, TiO 2 , TiSiO, TaO, Ta 2 O 5 , TaSiO, HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO, HfSiO, SrTiO, ZrSiON, HfZrTiO, HfZrSiON, HfZrLaO, or HfZrAlO.
of conductive or resistive materials · CPC title
in a gaseous ambient using an oxygen or a water vapour, e.g. oxidation through a layer (H10D64/01344 takes precedence) · CPC title
with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title
Electricity · mapped topic
Electricity · mapped topic
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