Analog capacitor

Patent metadata

Field	Value
Publication number	US-9893143-B2
Application number	US-201615266152-A
Country	US
Kind code	B2
Filing date	Sep 15, 2016
Priority date	Apr 4, 2016
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

An analog capacitor is disclosed. The analog capacitor may include a main analog capacitor, an interlayer insulating layer, and a plurality of stacked sub analog capacitors. The main analog capacitor may be formed over a semiconductor substrate. The interlayer insulating layer may be interposed between the semiconductor substrate and the main analog capacitor. The plurality of stacked sub analog capacitors may be inserted into the interlayer insulating layer.

First claim

What is claimed is:

1. An analog capacitor comprising:
a semiconductor substrate;
a first level capacitor formed on the semiconductor substrate;
a second level capacitor formed over the first level capacitor; and
a third level capacitor formed over the second level capacitor,
wherein each of the first to third level capacitors includes a first capacitor electrode and a second capacitor electrode insulated from each other to constitute a capacitor, and
the first capacitor electrodes of the first and second level capacitors are floating, and the first capacitor electrode of the third level capacitor is selectively coupled to an output voltage terminal, and
wherein the first capacitor electrodes of the first to third level capacitors are not electrically coupled to each other.

2. The analog capacitor of claim 1 , wherein the second capacitor electrodes of the first to third level capacitors are electrically coupled to each other.

3. The analog capacitor of claim 2 , wherein the second capacitor electrodes of the first to third level capacitors selectively receive a power supply voltage and a ground voltage.

4. The analog capacitor of claim 3 , wherein the second capacitor electrodes of the first to third level capacitors selectively receive the power supply voltage and the ground voltage according to a preset digital code.

5. The analog capacitor of claim 2 , wherein the second capacitor electrodes of the first to third level capacitors are electrically coupled to each other through a contact unit.

6. The analog capacitor of claim 1 , further comprising interlayer insulating layers interposed between the semiconductor substrate and the first level capacitor, between the first level capacitor and the second level capacitor, and between the second level capacitor and the third level capacitor.

7. The analog capacitor of claim 6 , wherein the second and third level capacitors are formed over corresponding interlayer insulating layers among the interlayer insulating layers to overlap the first level capacitor.

8. The analog capacitor of claim 1 , wherein the first level capacitor is formed of a first metal layer, the second level capacitor is formed of a second metal layer, and the third level capacitor is formed of a third metal layer.

9. The analog capacitor of claim 1 , wherein the first capacitor electrode in each of the first to third level capacitors is formed in a comb shape, and the second capacitor electrode in each of the first to third level capacitors is formed in a bar shape inserted between teeth of the comb-shaped first capacitor electrode.

10. An analog capacitor comprising:
a semiconductor substrate in which a first interlayer insulating layer is formed;
a first level capacitor formed over the first interlayer insulating layer and including a first capacitor electrode and a second capacitor electrode;
a second interlayer insulating layer formed over the first interlayer insulating layer over which the first level capacitor is formed;
a second level capacitor formed over the second interlayer insulating layer and including a first capacitor electrode and a second capacitor electrode;
a third interlayer insulating layer formed over the second interlayer insulating layer over which the second level capacitor is formed;
a third level capacitor formed over the third interlayer insulating layer and including a first capacitor electrode and a second capacitor electrode; and
a contact unit configured to electrically couple the second capacitor electrodes of the first, second and third level capacitors to each other,
wherein the first capacitor electrodes of the first to third level capacitors are not electrically coupled to each other.

11. The analog capacitor of claim 10 , wherein the first capacitor electrodes of the first and second level capacitors are floating, and the first capacitor electrode of the third level capacitor is selectively coupled to an output voltage terminal.

12. The analog capacitor of claim 10 , wherein the second capacitor electrodes of the first to third level capacitors selectively receive a power supply voltage and a ground voltage according to a preset digital code.

13. The analog capacitor of claim 10 , wherein the first to third level capacitors are formed to overlap each other.

14. The analog capacitor of claim 13 , wherein the first capacitor electrode in each of the first to third level capacitors is formed in a comb shape, and the second capacitor electrode in each of the first to third level capacitors is formed in a bar shape inserted between teeth of the comb-shaped first capacitor electrodes.

15. An analog capacitor comprising:
a semiconductor substrate;
a main analog capacitor formed over the semiconductor substrate;
an interlayer insulating layer interposed between the semiconductor substrate and the main analog capacitor; and
a plurality of stacked sub analog capacitors inserted into the interlayer insulating layer,
wherein the main analog capacitor and the plurality of stacked sub analog capacitors include a first capacitor electrode and a second electrode, respectively,
the first capacitor electrodes of the main analog capacitor and the plurality of stacked sub analog capacitors are not electrically coupled to each other.

16. The analog capacitor of claim 15 , wherein the first capacitor electrode is selectively coupled to an output terminal.

17. The analog capacitor of claim 16 , wherein the first capacitor electrodes of each of the sub analog capacitors are formed to overlap the first capacitor electrode of the main analog capacitor and the second capacitor electrodes are formed to overlap the second capacitor electrode of the main analog capacitor.

18. The analog capacitor of claim 17 , wherein the first capacitor electrodes of the sub analog capacitors are floating.

19. The analog capacitor of claim 17 , wherein the second capacitor electrodes of the main analog capacitor and the sub analog capacitors are electrically coupled to each other.

20. The analog capacitor of claim 15 , wherein the sub analog capacitors are insulated from each other.

Assignees

• Sk Hynix Inc

Inventors

• Cheon Jun Ho
• Ahn Chang Yong
• Kang Seok Joon

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H01L28/40 Primary

  Electricity · mapped topic

• H01L28/55

  Electricity · mapped topic

• H01L28/75

  Electricity · mapped topic

• H01L28/56

  Electricity · mapped topic