ESD protection circuit cell

Patent metadata

Field	Value
Publication number	US-9893054-B2
Application number	US-201514731622-A
Country	US
Kind code	B2
Filing date	Jun 5, 2015
Priority date	Dec 29, 2011
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd 1 and an output, and a driven device having an input and a second supply voltage Vdd 2 . The protection circuit includes a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus connected to Vdd 2 and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provided, from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus.

First claim

What is claimed is:

1. A protection circuit comprising:
a power bus;
a ground bus;
a first device from the group consisting of a P-diode and a gate-Vdd PMOS, the first device coupled between the power bus and an input of a driven device, the input of the driven device coupled to an output of a driving device, the first device having first and second N+ regions connected by a third N+ region with the third N+ region adjacent to the power bus; and
a second device from the group consisting of an N-diode and a grounded gate NMOS, the first and second devices arranged symmetrically about horizontal and vertical centerlines of the protection circuit, the second device coupled between the input of the driven device and the ground bus.

2. The protection circuit of claim 1 , wherein:
the first device is positioned near a PMOS of the driven device, the PMOS of the driven device connected to the input of the driven device, and
the second device is positioned near an NMOS of the driven device, the NMOS of the driven device connected to the input of the driven device.

3. The protection circuit of claim 1 , wherein:
the protection circuit further comprises a second unit cell having a second power bus connected to the power bus, the second unit cell having a second ground bus connected to the ground bus, the second unit cell having a first device thereof coupled between the second power bus and the input of the driven device, the second unit cell having a second device thereof coupled between the input of the driven device and the ground bus, the second unit cell placed adjacent the first unit cell.

4. The protection circuit of claim 1 , wherein:
the first device is a P diode having a P+ region between the first and second N+ regions, the P+ region connected to the input of the driven device and
the second device is an N diode having first and second connected P+ regions, and an N+ region near the first and second P+ regions, the N+ region connected to the input of the driven device.

5. The protection circuit of claim 4 , further comprising at least one dummy pattern adjacent the first or second N+ region of the first device and/or the first or second P+ region of the second device.

6. The protection circuit of claim 1 , wherein:
the first device is a gate-Vdd PMOS, and outer ones of the P+ regions are connected to the input of the driven device, and a gate electrode coupled to Vdd 2 , the gate electrode having portions between and above ones of the plurality of P+ regions, and
the second device is a gate grounded NMOS having first and second P+ regions connected by a third P+ region, and a plurality of N+ regions between the first and second P+ regions, outer ones of the N+ regions connected to the input of the driven device, and a gate electrode coupled to ground, the gate electrode having portions between and above ones of the plurality of N+ regions.

7. An integrated circuit (IC) comprising:
a driving device with a first supply voltage and an output,
a driven device having an input and a second supply voltage different from the first supply voltage,
a protection circuit for the IC, the protection circuit including:
a P-diode coupled between a first power bus and the input of the driven device, the P diode having first and second N+ regions connected by a third N+ region, and a P+ region between the first and second N+ regions, the P+ region connected to the input of the driven device, the input of the driven device coupled to the output of the driving device; and
an N-diode, the P diode and N diode arranged symmetrically about horizontal and vertical centerlines of the protection circuit, the N-diode coupled between the input of the driven device and a ground bus.

8. The IC of claim 7 , further comprising:
a second protection unit circuit abutted directly to the protection circuit, the second protection unit circuit having a second power bus configured to be connected to the first power bus, the second protection unit circuit having a second ground bus connected to the first ground bus, the second protection unit circuit having a first device thereof coupled between the second power bus and the input of the driven device, the second protection unit circuit having a second device thereof coupled between the input of the driven device and the ground bus.

9. The IC of claim 7 , wherein:
the N diode has first and second P+ regions connected by a third P+ region, and an N+ region between the first and second P+ regions, the P+ regions connected to ground, the N+ region connected to the input of the driven device.

10. The IC of claim 9 , further comprising
a second protection circuit configured to be abutted with the first protection circuit, the second protection circuit comprising:
a P diode having first and second connected N+ regions, and a P+ region between the first N+ region and one of the first and second N+ regions of the P diode of the first protection circuit, the P+ region to be connected to the input of the driven device, and
an N diode having first and second connected P+ regions, and an N+ region between the first P+ region and one of the first and second P+ regions of the N Diode of the first protection circuit, the N+ region connected to the input of the driven device.

11. The IC of claim 7 , further comprising a second protection circuit configured to be abutted with the first protection circuit, the second protection circuit comprising:
a gate-Vdd PMOS (GDPMOS) having first and second connected N+ regions, and a plurality of P+ regions between the first N+ region and one of the first and second P+ regions of the GDPMOS of the first protection circuit, and outer ones of the P+ regions connected to the input of the driven device, and a gate electrode having portions between and above ones of the plurality of P+ regions, and
a gate grounded NMOS (GGNMOS) having first and second connected P+ regions and a plurality of N+ regions between the first P+ region and one of the first and second P+ regions of the GGNMOS of the first protection cell, the P+ regions and an inner one of the N+ regions connected to ground, outer ones of the N+ regions connected to the input of the driven device, and a gate electrode coupled to ground.

12. An integrated circuit (IC), comprising:
a driving device with a first supply voltage and an output;
a driven device having an input and a second supply voltage different from the first supply voltage; and
a protection circuit including:
a gate-Vdd PMOS coupled between a first power bus and the input of the driven device, the gate-Vdd PMOS having first and second N+ regions connected by a third N+ region with the third N+ region adjacent to the first power bus, and a plurality of P+ regions between the first and second N+ regions, the input of the driven device coupled to the output of the driving device; and
a grounded gate NMOS (GGNMOS) coupled between the input of the driven device and a ground bus, the GGNMOS and gate-Vdd PMOS arranged symmetrically about horizontal and vertical centerlines of the protection circuit.

13. The IC of claim 12 wherein the first power bus abuts a power bus of the driven device.

14. The IC of claim 13 , wherein the ground bus of the protection circuit abuts a ground bus of the driven device.

15. The IC of claim 12 , further comprising:
a second protection circuit abutting the first protection circuit, the second protection circuit having a cell height that is the same as the cell height of the first protection circuit, the second protection circuit comprising:
a gate-Vdd PMOS, and
a grounded gate NMOS.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Bo Ting

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• H01L2924/00

  Electricity · mapped topic

• H01L27/0248

  Electricity · mapped topic