Advanced e-fuse structure with hybrid metal controlled microstructure

Patent metadata

Field	Value
Publication number	US-9893012-B2
Application number	US-201615083226-A
Country	US
Kind code	B2
Filing date	Mar 28, 2016
Priority date	Mar 28, 2016
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A structure and method for fabricating an e-Fuse device in a semiconductor device is described. A method for fabricating an e-Fuse device includes providing a trench structure including an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. An aspect ratio reducing layer is selectively formed in the anode and cathode regions of the trench while leaving the fuse element region of the trench substantially free of the aspect ratio reducing layer. The trench is filled with copper, both over the aspect ratio reducing layer in the anode and cathode regions and in the fuse element region. The copper is annealed to create a large grained copper structure in the anode and cathode regions and a fine grained copper structure in the fuse element. Another aspect of the invention is an e-Fuse device. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper layer and an aspect ratio reducing layer, and the fuse element is comprised of a fine grained copper structure.

First claim

Having described our invention, what we now claim is as follows:

1. A method for fabricating an e-Fuse device comprising:
providing a trench structure including an anode region, a cathode region and a fuse element region which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate, wherein the fuse element region has a smaller cross section and a higher aspect ratio than the anode and cathode regions;
depositing a liner layer over the trench structure;
selectively forming an aspect ratio reducing layer in the anode and cathode regions of the trench on the liner layer while leaving the fuse element region of the trench substantially free of the aspect ratio reducing layer;
filling the trench with a copper layer, both over the aspect ratio reducing layer in the anode and cathode regions and on the liner layer in the fuse element region;
creating respective large grained copper structures in the anode and cathode regions and a fine grained copper structure in the fuse element region by annealing the copper layer;
performing a planarization process to remove excess liner and copper layer over the dielectric layers outside the trench; and
depositing a metal cap layer over the copper layer in the trench in the entire anode, cathode and fuse element regions.

2. The method as recited in claim 1 , wherein the large grained copper structure is a bamboo structure and the fine grained structure is a polycrystalline structure.

3. The method as recited in claim 1 , wherein the aspect ratio is a ratio of a height of the trench divided by a width of the trench and the difference in aspect ratios between the fuse element region and the anode and cathode regions is greater than 0.5.

4. The method as recited in claim 1 , wherein the aspect ratio reducing layer is a conductive material.

5. The method as recited in claim 1 , wherein the aspect ratio reducing layer is a high EM-resistance material.

6. The method as recited in claim 1 , wherein the aspect ratio reducing layer is selected from the group consisting of W, Co, Rh, Ru, Au, Ag and Al.

7. The method as recited in claim 1 , wherein the metal cap layer is selected from the group consisting of Co, W, Rh, and Ru and their alloy materials.

8. The method as recited in claim 1 , wherein a cathode is formed in the cathode region, an anode is formed in the anode region and a fuse element is formed in the fuse element region.

9. The method as recited in claim 7 , further comprising applying an electric current to the e-Fuse device, wherein the metal cap layer controls the electromigration properties preventing surface diffusion electromigration in the copper layer.

10. A method for fabricating an e-Fuse device comprising:
providing a trench structure including an anode region, a cathode region and a fuse element region which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate, wherein the fuse element region has a smaller cross section and a higher aspect ratio than the anode and cathode regions;
selectively forming an aspect ratio reducing layer in the anode and cathode regions of the trench while leaving the fuse element region of the trench substantially free of the aspect ratio reducing layer;
filling the trench with a copper layer, both over the aspect ratio reducing layer in the anode and cathode regions and in the fuse element region;
creating respective large grained copper structures in the anode and cathode regions and a fine grained copper structure in the fuse element region by annealing the copper layer;
wherein selectively forming an aspect ratio reducing layer in the anode and cathode regions of the trench while leaving the fuse element region of the trench substantially free of the aspect ratio reducing layer comprises:
protecting the fuse element region with a block out mask;
depositing the aspect ratio reducing layer in the anode and cathode regions; and
reducing the thickness of the aspect ratio reducing layer using an etch step.

11. A method for fabricating an e-Fuse device comprising:
providing a trench structure including an anode region, a cathode region and a fuse element region which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate, wherein the fuse element region has a smaller cross section and a higher aspect ratio than the anode and cathode regions;
selectively forming an aspect ratio reducing layer in the anode and cathode regions of the trench while leaving the fuse element region of the trench substantially free of the aspect ratio reducing layer;
filling the trench with a copper layer, both over the aspect ratio reducing layer in the anode and cathode regions and in the fuse element region;
creating respective large grained copper structures in the anode and cathode regions and a fine grained copper structure in the fuse element region by annealing the copper layer;
wherein selectively forming an aspect ratio reducing layer in the anode and cathode regions of the trench while leaving the fuse element region of the trench substantially free of the aspect ratio reducing layer comprises:
protecting the fuse element region with a block out mask;
depositing the aspect ratio reducing layer in the anode and cathode regions; and
reflowing the aspect ratio reducing layer using a thermal reflow process.

12. A method for fabricating an e-Fuse device comprising:
providing a trench structure including an anode region, a cathode region and a fuse element region which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate, wherein the fuse element region has a smaller cross section and a higher aspect ratio than the anode and cathode regions;
selectively forming an aspect ratio reducing layer in the anode and cathode regions of the trench while leaving the fuse element region of the trench substantially free of the aspect ratio reducing layer;
filling the trench with a copper layer, both over the aspect ratio reducing layer in the anode and cathode regions and in the fuse element region;
creating respective large grained copper structures in the anode and cathode regions and a fine grained copper structure in the fuse element region by annealing the copper layer;
wherein the Cu layer forms fifty to seventy percent of the thickness of the trench in the anode and cathode regions and a remainder of thickness of the trench in the anode and cathode regions filled by the aspect ratio reducing layer.

Assignees

• IBM

Inventors

• Edelstein Daniel C
• Yang Chih Chao

Classifications

• H10P95/80

  Electrical treatments, e.g. for electroforming · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/493 Primary

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H01L23/5256 Primary

  Electricity · mapped topic