Semiconductor module

Patent metadata

Field	Value
Publication number	US-9893006-B2
Application number	US-201615338495-A
Country	US
Kind code	B2
Filing date	Oct 31, 2016
Priority date	Dec 16, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A semiconductor module includes a plurality of semiconductor chips that include gate electrodes on front surfaces, a gate terminal that receives a control signal from outside, and a print substrate. The print substrate includes a gate wiring layer that separates the control signal that is input into the gate terminal and passes the control signal to the gate electrodes of the semiconductor chips, and a cross-sectional area of the gate wiring layer becomes larger as the gate wiring layer gets closer to the gate terminal from the gate electrodes.

First claim

What is claimed is:

1. A semiconductor module comprising:
a plurality of semiconductor chips including gate electrodes on front surfaces;
a gate terminal configured to receive a control signal from outside; and
a print substrate including a gate wiring layer for causing the control signal received by the gate terminal to separate and pass to the gate electrodes of the plurality of semiconductor chips, wherein a cross-sectional area of the gate wiring layer becomes larger as the cross-sectional area gets closer to the gate terminal from the gate electrodes.

2. The semiconductor module according to claim 1 , further comprising:
a drain plate made of conductive material; and
a stacked substrate including an insulation plate and a circuit plate stacked one on another,
wherein the plurality of semiconductor chips further include source electrodes on the front surfaces and drain electrodes on back surfaces,
the plurality of semiconductor chips and the stacked substrate are located on a front surface of the drain plate,
the drain plate is electrically connected to the drain electrodes, and
the gate wiring layer is electrically connected to the gate terminal via the circuit plate.

3. The semiconductor module according to claim 2 , wherein
the gate terminal is located on the circuit plate.

4. The semiconductor module according to claim 1 , wherein
the cross-sectional area of the gate wiring layer becomes larger, each time the gate wiring layer branches, as the gate wiring layer gets closer to the gate terminal from the gate electrodes.

5. The semiconductor module according to claim 1 , wherein
in the gate wiring layer, a line for transmitting the control signal becomes thicker as the line gets closer to the gate terminal from the gate electrodes.

6. The semiconductor module according to claim 1 , wherein
in the gate wiring layer, a line for transmitting the control signal becomes wider as the line gets closer to the gate terminal from the gate electrodes.

7. The semiconductor module according to claim 5 , wherein
in the gate wiring layer, a thickness of the line for transmitting the control signal is from 0.1 mm to 1.65 mm around the gate electrodes.

8. The semiconductor module according to claim 6 , wherein
in the gate wiring layer, a width of the line for transmitting the control signal is from 0.1 mm to 1.65 mm around the gate electrodes.

9. The semiconductor module according to claim 4 , wherein the gate wiring layer has a tree structure.

Assignees

• Fuji Electric Co Ltd

Inventors

• Inaba Tetsuya
• Ikeda Yoshinari

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W76/161

  Containers comprising no base · CPC title

• H10W76/15

  Containers comprising an insulating or insulated base · CPC title

• H10W40/255

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title