Package substrate and flip-chip package circuit including the same

Patent metadata

Field	Value
Publication number	US-9893003-B2
Application number	US-201414520767-A
Country	US
Kind code	B2
Filing date	Oct 22, 2014
Priority date	Jun 17, 2014
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

This disclosure provides a package substrate, a flip-chip package circuit, and their fabrication methods. The package substrate includes: a first wiring layer having a first dielectric material layer and a first metal wire protruding from the first dielectric material layer; a conductive pillar layer formed on the first wiring layer and including a molding compound layer, a second dielectric material layer formed on the molding compound layer, and a metal pillar connected to the first metal wire; a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the metal pillar; and a protection layer formed on the second wiring layer.

First claim

What is claimed is:

1. A package substrate comprising:
a first wiring layer, comprising:
a first dielectric material layer; and
a first metal wire, protruding downward from the first dielectric material layer,
wherein the first dielectric material layer has a protrusion part laterally surrounding the first metal wire and not exceeding a bottom of the first metal wire, and said protrusion part has an inner flat side wall directly adjacent to said first metal wire and an outer concave side wall corresponding to a decreasing width of the protrusion part from top to bottom;

a conductive pillar layer, formed on the first wiring layer, comprising:
a molding compound layer;
a second dielectric material layer, formed on the molding compound layer; and
a solid metal pillar, directly connected to the first metal wire, wherein the solid metal pillar penetrates through the molding compound layer and the second dielectric layer;

a second wiring layer, formed on the conductive pillar layer, comprising a second metal wire directly connected to the solid metal pillar; and
a protection layer, formed on the second wiring layer.

2. The package substrate according to claim 1 , wherein the package substrate is a flip-chip chip size package (FCCSP) substrate.

3. The package substrate according to claim 1 , wherein the first metal wire has a side surface completely covered by the first dielectric material layer.

4. A flip-chip package circuit comprising:
a first wiring layer, comprising:
a first dielectric material layer; and
a first metal wire protruding downward from the first dielectric material layer,
wherein the first dielectric material layer has a protrusion part laterally surrounding the first metal wire and not exceeding a bottom of the first metal wire, and said protrusion part has an inner flat side wall directly adjacent to said first metal wire and an outer concave side wall corresponding to a decreasing width of the protrusion part from top to bottom;

a conductive pillar layer, formed on the first wiring layer, comprising:
a molding compound layer;
a second dielectric material layer, formed on the molding compound layer; and
a solid metal pillar, directly connected to the first metal wire;

a second wiring layer formed on the conductive pillar layer, comprising a second metal wire directly connected to the solid metal pillar;
a protection layer, formed on the second wiring layer and having an opening exposing the second metal wire;
a circuit chip, disposed under the first wiring layer and electrically connected to the first metal wire; and
a printed circuit board, disposed on the protection layer and electrically connected to the second metal wire through the opening of the protection layer.

5. The flip-chip package circuit according to claim 4 , wherein the first metal wire has a side surface completely covered by the first dielectric material layer.

6. The package substrate according to claim 1 , wherein the protrusion part partially covers and partially exposes a side surface of the first metal wire.

7. The package substrate according to claim 1 , wherein the conductive pillar layer is formed on the first dielectric material layer and the first metal wire.

8. The package substrate according to claim 4 , wherein the protrusion part partially covers and partially exposes a side surface of the first metal wire.

9. The package substrate according to claim 4 , wherein the conductive pillar layer is formed on the first dielectric material layer and the first metal wire.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Hsu Che Wei
• Hsu Shih Ping

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title