Device and method for reducing contact resistance of a metal

Patent metadata

Field	Value
Publication number	US-9892963-B2
Application number	US-201514879992-A
Country	US
Kind code	B2
Filing date	Oct 9, 2015
Priority date	Jul 31, 2012
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A method of fabricating an integrated circuit includes depositing a cap layer on a substrate; depositing a dielectric layer on the cap layer; and forming a trench in the dielectric layer. The method further includes depositing a tantalum nitride (TaN) layer on a sidewall of the trench such that the TaN layer has a greater concentration of nitrogen than tantalum. The method further includes depositing a tantalum (Ta) layer on the TaN layer using physical vapor deposition (PVD); and depositing a metal layer over the Ta layer.

First claim

What is claimed is:

1. A method of fabricating an integrated circuit, the method comprising:
depositing a cap layer on a substrate;
depositing a dielectric layer on the cap layer;
forming a trench in the dielectric layer;
depositing a tantalum nitride (TaN) layer on a sidewall of the trench such that the TaN layer has a greater concentration of nitrogen than tantalum;
depositing a tantalum (Ta) layer on the TaN layer using physical vapor deposition (PVD); and
depositing a metal layer over the Ta layer, wherein an overall N/Ta ratio of the TaN and Ta layers ranges from about 0.6 to about 1.0.

2. The method of claim 1 , wherein the TaN layer is deposited using atomic layer deposition (ALD), and an N/Ta ratio of the TaN layer ranges from about 2.3 to about 2.6.

3. The method of claim 1 , wherein the depositing of the TaN layer includes plasma sputtering a Ta target with a nitrogen (N 2 ) flow of at least 20 Standard Cubic Centimeters per Minute (sccm).

4. The method of claim 1 , wherein the TaN layer is deposited to have a thickness ranging from about 5 to about 10 angstrom (Å).

5. The method of claim 1 , wherein the Ta layer is deposited to have a thickness ranging from about 50 to about 100 Å.

6. The method of claim 1 , wherein the metal layer includes copper.

7. The method of claim 1 , wherein the TaN layer is deposited using physical vapor deposition (PVD).

8. A method of fabricating an integrated circuit, the method comprising:
depositing a cap layer on a substrate;
depositing a dielectric layer on the cap layer;
forming a trench in the dielectric layer;
depositing a tantalum nitride (TaN) layer on a side wall of the trench using physical vapor deposition (PVD) such that the TaN layer has a greater concentration of nitrogen than tantalum;
depositing a tantalum (Ta) layer on the TaN layer using PVD; and
depositing a metal layer over the Ta layer, wherein an overall carbon (C) concentration of the TaN and Ta layers is lower than about 0.2 percent (%).

9. The method of claim 8 , wherein the depositing of the TaN layer includes plasma sputtering a Ta target with a nitrogen (N 2 ) flow of at least 20 Standard Cubic Centimeters per Minute (sccm).

10. The method of claim 9 , wherein the N 2 flow ranges from about 20 sccm to about 40 sccm.

11. The method of claim 9 , wherein the depositing of the TaN layer further includes an argon (Ar) flow ranging from about 4 sccm to about 50 sccm, a DC power ranging from about 3 kW to about 15 kW, and an AC power ranging from about 75 W to about 250 W.

12. The method of claim 8 , wherein the TaN layer is deposited to have a thickness ranging from about 10 to about 20 angstrom (Å).

13. The method of claim 8 , wherein the Ta layer is deposited to have a thickness ranging from about 50 to about 100 Å.

14. The method of claim 8 , wherein the metal layer includes copper.

15. The method of claim 8 , wherein an overall N/Ta ratio of the TaN layer and the Ta layer ranges from 0.6 to 1.0.

16. A method of fabricating an integrated circuit, the method comprising:
depositing a cap layer on a substrate;
depositing a dielectric layer on the cap layer;
forming a trench in the dielectric layer;
depositing a first tantalum nitride (TaN) layer on a side wall of the trench using atomic layer deposition (ALD) such that the first TaN layer has a greater concentration of nitrogen than tantalum;
depositing a tantalum (Ta) layer on the first TaN layer using physical vapor deposition (PVD); and
depositing a copper-containing metal layer over the Ta layer, wherein an overall N/Ta ratio of the first TaN layer and the Ta layer ranges from 0.6 to 1.0.

17. The method of claim 16 , wherein an N/Ta ratio of the first TaN layer ranges from about 2.3 to about 2.6.

18. The method of claim 16 , wherein the first TaN layer is deposited to have a thickness ranging from about 5 to about 10 angstrom (Å), and the Ta layer is deposited to have a thickness ranging from about 50 to about 100 Å.

19. The method of claim 16 , further comprising:
depositing a second TaN layer between the first TaN layer and the Ta layer using PVD.

20. The method of claim 16 , wherein an overall carbon (C) concentration of the TaN and Ta layers is about 0.2 percent (%) to 1%.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Ya Lien
• Su Hung Wen
• Lee Kuei Pin
• Lin Yu Hung
• Chang Yu Min

Classifications

• H10P14/432

  using selective deposition · CPC title

• H10P14/44

  Physical vapour deposition [PVD] · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title