Electrically erasable programmable non-volatile memory cell structure

Patent metadata

Field	Value
Publication number	US-9892928-B2
Application number	US-201614989801-A
Country	US
Kind code	B2
Filing date	Jan 7, 2016
Priority date	Jan 7, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A NVM cell structure includes a semiconductor substrate having a first conductivity type, a first well region having a second conductivity type, a floating gate transistor and an erase gate region. The first well region is disposed on a first OD region of the semiconductor substrate. The erase gate region disposed on a second OD region of the semiconductor substrate includes a first doped region and at least one second doped region having the second conductivity type. The first doped region is disposed in semiconductor substrate and covers the second OD region, and the second doped region is disposed in the first doped region. The first doped region encompasses the second doped region, and a doping concentration of the second doped region is larger than a doping concentration of the first doped region.

First claim

What is claimed is:

1. A non-volatile memory (NVM) cell structure, comprising:
a semiconductor substrate having a first conductivity type, and the substrate has a first oxide define (OD) region and a second OD region separated from each other;
a first well region disposed in the first OD region of the semiconductor substrate, wherein the first well region has a second conductivity type;
a floating gate transistor on the first well region, wherein the floating gate transistor comprises a floating gate and a floating gate dielectric layer disposed between the floating gate and the first well region, and the floating gate comprises a first part overlapping the first OD region and a second part overlapping the second OD region; and
an erase gate region on the second OD region, wherein the erase gate region comprises a first doped region disposed in the second OD region and covering the second OD region, two second doped regions disposed in the first doped region, and an erase gate dielectric layer between the first doped region and the second part of the floating gate, wherein the first doped region and each second doped region have the second conductivity type, and a doping concentration of each second doped region is larger than a doping concentration of the first doped region, and wherein the second doped regions are disposed at two sides of the second part of the floating gate, and a combination of the second doped regions and the second part of the floating gate totally covers the first doped region.

2. The NVM cell structure according to claim 1 , further comprising an isolation structure, disposed in the semiconductor substrate, and the isolation structure defining the first OD region and the second OD region.

3. The NVM cell structure according to claim 1 , wherein the erase gate region further comprises a second well region, disposed in the semiconductor substrate under the first doped region, and a top of the second well region being in direct contact with the first doped region, wherein the second well region has the first conductivity type, and a doping concentration of the second well region is larger than a doping concentration of the semiconductor substrate.

4. The NVM cell structure according to claim 3 , further comprising an intermediate well region, disposed in the semiconductor substrate between the first OD region and the second OD region, and two sides of the intermediate well region being in direct contact with the first well region and the second well region respectively, wherein the intermediate well region has the first conductivity type, and a doping concentration of the intermediate well region is larger than the doping concentration of the second well region.

5. The NVM cell structure according to claim 3 , further comprising a first deep well region, disposed in the semiconductor substrate under the first well region and the second well region, wherein the first deep well region has the second conductivity type.

6. The NVM cell structure according to claim 5 , further comprising a second deep well region, disposed in the semiconductor substrate between the first well region and the first deep well region and between the second well region and the first deep well region, wherein the second deep well region has the first conductivity type, and a doping concentration of the second deep well region is larger than the doping concentration of the semiconductor substrate.

7. The NVM cell structure according to claim 1 , further comprising an intermediate well region, disposed in the semiconductor substrate between the first OD region and the second OD region, and the intermediate well region being in direct contact with the first well region, wherein a doping concentration of the intermediate well region is larger than a doping concentration of the semiconductor substrate.

8. The NVM cell structure according to claim 7 , further comprising a first deep well region and a second deep well region, disposed in the semiconductor substrate under the first well region, and the second deep well region being disposed between the first well region and the first deep well region and between the intermediate well region and the first deep well region, wherein the first deep well region has the second conductivity type, the second deep well region has the first conductivity type, and a doping concentration of the second deep well region is larger than the doping concentration of the semiconductor substrate.

9. The NVM cell structure according to claim 1 , wherein an overlapping area between the floating gate and the first OD region is larger than an overlapping area between the floating gate and the second OD region.

10. The NVM cell structure according to claim 1 , wherein the floating gate crosses the first doped region.

11. The NVM cell structure according to claim 1 , wherein an edge of the floating gate is disposed right on the first doped region.

12. The NVM cell structure according to claim 1 , wherein the floating gate transistor further comprising a third doped region and a fourth doped region disposed in the first well region at two sides of the floating gate, wherein the third doped region and the fourth doped region both have the first conductivity type.

13. The NVM cell structure according to claim 12 , further comprising a select transistor disposed on the first OD region and electrically connected to the floating gate transistor in series through the fourth doped region.

14. The NVM cell structure according to claim 1 , wherein the first conductivity type is p-type, and the second conductivity type is n-type.

Assignees

• Ememory Technology Inc

Inventors

• Li Chun Hsiao
• Chen wei ren
• Lee Wen Hao

Classifications

• H01L21/28273 Primary

  Electricity · mapped topic

• H01L29/42328

  Electricity · mapped topic

• H01L27/11558

  Electricity · mapped topic

• H01L29/7883

  Electricity · mapped topic

• H10D64/037

  comprising charge-trapping insulators · CPC title