Fast scan to detect bit line discharge time

Patent metadata

Field	Value
Publication number	US-9892791-B2
Application number	US-201615184939-A
Country	US
Kind code	B2
Filing date	Jun 16, 2016
Priority date	Jun 16, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to a voltage level for sensing erased memory cells. The threshold current may be set based on a chip temperature and/or a particular number of bit errors that occurred during a prior sensing operation.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory array including a plurality of memory cells connected to a control line; and
a control circuit configured to acquire a threshold current corresponding with a number of memory cells in a conducting state and sum a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells sensed to be in a conducting state, the control circuit configured to delay a ramping in a voltage applied to the control line until detection that the sum of the first set of detection currents is greater than the threshold current, the control line comprises a word line.

2. The apparatus of claim 1 , wherein:
the control circuit configured to increase the voltage applied to the word line using a word line voltage ramp.

3. The apparatus of claim 2 , wherein:
the control circuit configured to increase the voltage applied to the word line using a word line voltage ramp from a first voltage to a second voltage greater than the first voltage in response to detecting that the sum of the first set of detection currents is greater than the threshold current.

4. The apparatus of claim 1 , wherein:
the control circuit configured to determine the threshold current based on a number of bit errors that occurred during a prior sensing of the plurality of memory cells.

5. The apparatus of claim 1 , wherein:
the control circuit configured to determine the threshold current based on a chip temperature.

6. The apparatus of claim 1 , wherein:
the control circuit configured to set the control line to a first voltage and sum the first set of detection currents while the control line is set to the first voltage.

7. The apparatus of claim 6 , wherein:
the first voltage corresponds with a voltage level for sensing erased memory cells.

8. The apparatus of claim 1 , wherein:
the control circuit configured to perform a read operation while the first set of detection currents is summed.

9. The apparatus of claim 1 , wherein:
the control circuit configured to perform a program verify operation while the first set of detection currents is summed.

10. The apparatus of claim 1 , wherein:
the memory array comprises a three-dimensional memory array.

11. The apparatus of claim 1 , wherein:
the memory array comprises a non-volatile memory that is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.

12. A method, comprising:
determining a threshold current corresponding with a number of conducting memory cells;
setting a word line connected to a plurality of memory cells to a first voltage;
summing a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to the first voltage; and
delaying a ramping of the word line to a second voltage greater than the first voltage in response to detecting that the sum of the first set of detection currents is greater than the threshold current.

13. The method of claim 12 , further comprising:
determining the threshold current based on a number of bit errors that occurred during a prior sensing of the plurality of memory cells.

14. The method of claim 12 , further comprising:
determining the threshold current based on a chip temperature.

15. The method of claim 12 , wherein:
the ramping of the word line to the second voltage greater than the first voltage includes increasing a voltage applied to the word line.

16. The method of claim 15 , wherein:
the first voltage corresponds with a first voltage level for sensing an erased data state; and
the second voltage corresponds with a second voltage level for sensing a data state different from the erased data state.

17. The method of claim 12 , further comprising:
sensing a second set of memory cells of the plurality of memory cells different from the first set of memory cells while the word line is set to the second voltage.

18. The method of claim 12 , further comprising:
performing a read operation on the plurality of memory cells while the first set of detection currents is summed.

19. An apparatus, comprising:
a plurality of memory cells connected to a word line; and
a control circuit configured to determine a threshold current corresponding with a number of erased memory cells and sum a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells sensed to be in a conducting state, the control circuit configured to delay a ramping in a voltage applied to the word line until detection that the sum of the first set of detection currents is greater than the threshold current.

20. The apparatus of claim 19 , wherein:
the control circuit configured to determine the threshold current based on a number of bit errors that occurred during a prior sensing of the plurality of memory cells; and
the plurality of memory cells comprise ReRAM memory cells.

21. A system, comprising:
a plurality of memory cells connected to a word line;
means for summing a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells sensed to be in a conducting state;
means for detecting that the sum of the first set of detection currents is greater than a threshold current corresponding with a particular number of conducting memory cells; and
a control circuit configured to delay a ramping in a voltage applied to the word line until detection that the sum of the first set of detection currents is greater than the threshold current.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Li Yen Lung
• Yuh Jong
• Huynh Jonathan
• Tseng Tai Yuan
• Kim Kwang Ho
• Nguyen Qui

Classifications

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title