Methods for checking dependencies of data units and apparatuses using the same

Patent metadata

Field	Value
Publication number	US-9892484-B2
Application number	US-201615141767-A
Country	US
Kind code	B2
Filing date	Apr 28, 2016
Priority date	Nov 17, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A memory access request associated with a data unit is received from a first thread of a pixel shader. A processing status associated with the data unit is obtained from a window buffer. It is determined whether the data unit is being processed by a second thread. If so, a rejection procedure is performed to avoid the first thread gaining to access an attribute value associated with the data unit from/to a DRAM (Dynamic Random Access Memory). Otherwise, an acknowledgement procedure is performed to grant the first thread to access the attribute value associated with the data unit from/to the DRAM.

First claim

What is claimed is:

1. A method for checking dependencies of data units, comprising:
receiving a memory access request associated with a data unit from a first thread of a pixel shader;
obtaining a processing status associated with the data unit from a plurality of bit values of a cell of a window buffer, wherein each bit value of the cell is associated with one data unit at specific coordinates of a 2D (two-dimensional) image;
determining whether the data unit is being processed by a second thread by inspecting the corresponding bit value of the cell;
if so, performing a rejection procedure to avoid the first thread gaining to access an attribute value associated with the data unit from/to a DRAM (Dynamic Random Access Memory); and
otherwise, performing an acknowledgement procedure to grant the first thread to access the attribute value associated with the data unit from/to the DRAM,
wherein the memory access request comprises the coordinates at which the data unit is situated in the 2D image, the window buffer is a 1R1W- or 2R2W-type SRAM (Static Random Access Memory) and the step for obtaining a processing status associated with the data unit from a window buffer further comprises:
calculating a cell index according to the coordinates;
reading whole cell data corresponding to the cell index from the 1R1W- or 2R2W-type SRAM; and
obtaining the processing status associated with the data unit from the whole cell data.

2. The method of claim 1 , wherein the corresponding bit value being logic “1” indicates that the data unit is being processed by the second thread and the bit value being logic “0” indicates that the data unit has not been processed by any thread.

3. The method of claim 1 , wherein addressing information of the processing status associated the data unit conforms to its coordinates in the 2D image.

4. The method of claim 1 , wherein the rejection procedure further comprises:
replying with a rejection message to the first thread; and
writing the original cell data into an address corresponding to the cell index of the 1R1W- or 2R2W-type SRAM.

5. The method of claim 1 , wherein the acknowledgement procedure further comprises:
replying with an acknowledgement to the first thread;
updating the processing status associated with the data unit to indicate that the data unit is being processed by the first thread; and
writing the updated cell data into an address corresponding to the cell index of the 1R1W- or 2R2W-type SRAM.

6. The method of claim 1 , wherein the data unit is a pixel, a quad or a tile.

7. The method of claim 1 , wherein the processing status associated with the data unit, which is stored in the window buffer, is obtained through an arbiter.

8. An apparatus for checking dependencies of data units, comprising:
a window buffer; and
a window checker, coupled to the window buffer, receiving a memory access request associated with a data unit from a first thread of a pixel shader; obtaining a processing status associated with the data unit from a plurality of bit values of a cell of a window buffer, wherein each bit value of the cell is associated with one data unit at specific coordinates of a 2D (two-dimensional) image; determining whether the data unit is being processed by a second thread by inspecting the corresponding bit value of the cell; if so, performing a rejection procedure to avoid the first thread gaining to access an attribute value associated with the data unit from/to a DRAM (Dynamic Random Access Memory); and otherwise, performing an acknowledgement procedure to grant the first thread to access the attribute value associated with the data unit from/to the DRAM,
wherein the memory access request comprises the coordinates at which the data unit is situated in the 2D image, the window buffer is a 1R1W- or 2R2W-type SRAM (Static Random Access Memory) and the window checker calculates a cell index according to the coordinates; reading whole cell data corresponding to the cell index from the 1R1W- or 2R2W-type SRAM; and obtains the processing status associated with the data unit from the whole cell data.

9. The apparatus of claim 8 , wherein the bit value being logic “1” indicates that the data unit is being processed by the second thread and the bit value being logic “0” indicates that the data unit has not been processed by any thread.

10. The apparatus of claim 8 , wherein addressing information of the processing status associated the data unit conforms to its coordinates in the 2D image.

11. The apparatus of claim 8 , wherein the rejection procedure further comprises:
replying with a rejection message to the first thread; and
writing the original cell data into an address corresponding to the cell index of the 1R1W- or 2R2W-type SRAM.

12. The apparatus of claim 8 , wherein the acknowledgement procedure further comprises:
replying with an acknowledgement to the first thread;
updating the processing status associated with the data unit to indicate that the data unit is being processed by the first thread; and
writing the updated cell data into an address corresponding to the cell index of the 1R1W- or 2R2W-type SRAM.

13. The apparatus of claim 8 , wherein the data unit is a pixel, a quad or a tile.

14. The apparatus of claim 8 , wherein the processing status associated with the data unit, which is stored in the window buffer, is obtained through an arbiter.

Assignees

• Via Alliance Semiconductor Co Ltd

Inventors

• Xiao Heng
• Liang Ying
• Que Heng

Classifications

• G06T2200/24

  involving graphical user interfaces [GUIs] · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T11/40

  Filling planar surfaces by adding surface attributes, e.g. adding colours or textures · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title