Receive mode upon expiration of UART transmit start BIT delay

Patent metadata

Field	Value
Publication number	US-9892080-B2
Application number	US-201514967959-A
Country	US
Kind code	B2
Filing date	Dec 14, 2015
Priority date	Feb 19, 2014
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

Signaling to control transmit/receive mode transitions of a serial half-duplex transceiver coupled externally to an integrated circuit is provided by the integrated circuit separately from a host processor of the integrated circuit with which the transceiver communicates. This can avoid slow transceiver turn-around times that may be associated with host processor control of the mode transitions.

First claim

What is claimed is:

1. A process of operating an integrated circuit comprising:
monitoring, in logic circuitry separate from host processor circuitry, a transmit data output of a UART for a start bit;
starting a timer in the logic circuitry and selecting a transmit mode output from the logic circuitry upon monitoring a start bit on the transmit data output;
selecting a receive mode output from the logic circuitry upon expiration of the timer;
beginning a delay before the selecting;
monitoring the transmit data output of the UART for another start bit during the delay; and
proceeding to the selecting upon expiration of the delay.

2. The process of claim 1 including, upon expiration of the timer, beginning a delay before the selecting.

3. The process of claim 1 including, upon expiration of the timer, beginning a delay before the selecting and monitoring the transmit data output of the UART for another start bit.

4. A process of operating an integrated circuit comprising:
monitoring, in logic circuitry separate from host processor circuitry, a transmit data output of a UART for a start bit;
starting a timer in the logic circuitry and selecting a transmit mode output from the logic circuitry upon monitoring a start bit on the transmit data output;
selecting a receive mode output from the logic circuitry upon expiration of the timer;
beginning a delay before the selecting;
monitoring the transmit data output of the UART for another start bit during the delay; and
again starting the timer in the logic circuitry and selecting the transmit mode output from the logic circuitry upon monitoring another start bit on the transmit data output.

Assignees

• Texas Instruments Inc

Inventors

• Patton Jr Schuyler T
• Prakash Punya
• Watkins Melissa Marie
• Mohammad Saqib Nadeem
• Griffis Bradley James

Classifications

• H04L5/16 Primary

  Half-duplex systems; Simplex/duplex switching; Transmission of break signals {non-automatically inverting the direction of transmission} · CPC title

• G06F13/4072 Primary

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title

• G06F2213/0002

  Serial port, e.g. RS232C · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title