Management of random cache read operations

Patent metadata

Field	Value
Publication number	US-9892032-B2
Application number	US-201313761700-A
Country	US
Kind code	B2
Filing date	Feb 7, 2013
Priority date	Feb 7, 2013
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A method and system are disclosed that monitor and control random cache read operations. Random cache read operation may occur until the expiration of a timer. Upon expiration of the timer, the current random cache read sequence is terminated and new received read commands will not use this sequence. A flash controller may either use a page read operation or initiate a new random cache read sequence.

First claim

We claim:

1. A method for command operation management comprising:
in a memory system having blocks stored in non-volatile storage and a controller in communication with the non-volatile storage, the controller is configured for:
receiving a first page read operation that comprises a sense phase and a transfer phase, wherein the sense phase occurs first and at least a read access time follows before the transfer phase;
implementing a timer wherein a second sense phase from a second page read operation occurs unless the timer has expired, wherein a value of the timer depends on a transfer size for a pending transfer phase;
executing a random cache read operation before the timer expires that includes executing the transfer phase from the first page read operation after the second sense phase; and
executing a page read operation when the timer expires before the second sense phase that includes executing the transfer phase from the first page read operation before the second sense phase.

2. The method of claim 1 wherein the receiving by the controller is from a host.

3. The method of claim 1 wherein the timer is configurable.

4. The method of claim 3 wherein the timer is optimized during page read operations.

5. The method of claim 4 wherein the timer is initially set as the read access time.

6. The method of claim 3 wherein firmware for the memory system can fine tune the timer.

7. The method of claim 3 wherein the timer can be disabled by setting its value to zero.

8. The method of claim 1 further comprising:
implementing, after the second sense phase, the timer wherein a third sense phase from a third page read operation occurs unless the timer has expired; and
executing the transfer phase from the second page read operation after the third sense phase, or when the timer expires before the third sense phase the transfer phase from the second page read operation is executed before the third sense phase.

9. The method of claim 1 wherein the random cache read operation continues even when a queue of read operations is empty and until the timer expires, further wherein the random cache read operation includes waiting for a next page read operation before conducting a transfer operation.

10. The method of claim 9 wherein the random cache read operation is terminated upon expiration of the timer, further wherein expiration of the timer before receipt of another read operation will result in implementation of the transfer operation.

11. A memory system comprising:
a non-volatile storage having an array of memory blocks storing data that is associated with logical block addresses (LBAs); and
a controller in communication with the blocks, the controller configured to:
receive a first page read operation that includes a first sense command and a first transfer command;
activate a timer during which a random cache read operation is used for handling subsequent commands, wherein expiration of the timer before receipt of one of the subsequent commands stops the random cache read operation and implements a page read operation;
generate, when the timer has not expired and the random cache read operation continues, a second sense command from a second page read operation; and
generate, when the timer has expired before receipt of the second sense command, the first transfer command from the first page read operation as part of the page read operation.

12. The memory system of claim 11 wherein the memory system comprises a flash memory or a solid state memory.

13. The memory system of claim 11 further comprising:
activate the timer upon receipt of the second sense command; and
generate, when the timer has not expired, a third sense command from a third page read operation, or generate, when the timer has expired, a second transfer command from the second page read operation.

14. The memory system of claim 11 wherein the timer is configurable.

15. The memory system of claim 14 wherein the timer is optimized during page read operations.

16. The memory system of claim 15 wherein the timer is initially set as the read access time before being optimized.

17. The memory system of claim 11 wherein the random cache read operation is only terminated upon expiration of the timer even when a queue of read operations is empty, further wherein expiration of the timer before receipt of another read operation will result in implementation of the transfer operation.

18. A method for operating a memory system comprising:
in a non-volatile storage device having a controller and blocks of memory, the controller is configured for:
receiving a first page read operation;
executing a first sense phase from the first page read operation;
initiating a timer;
executing a second sense command before executing a first transfer command from the first page read operation when a second page read operation is received before expiration of the timer; and
executing, when the timer has expired before receipt of the second sense command, a first transfer command from the first page read operation before executing a second page read operation.

19. The method of claim 18 wherein random cache read operation is maintained as long as the timer has not expired and even when a queue of read operations is empty.

20. The method of claim 19 wherein random cache read operation is stopped after the timer has expired.

21. A method for operating a memory system comprising:
in a non-volatile storage device having a controller and blocks of memory, the controller is configured for:
implementing random cache read operations for executing multiple sense phases from multiple page read operations before executing corresponding transfer phases;
continuing the random cache read operations even when there are no pending page read operations; and
stopping random cache read operations and switching to page read operations, upon expiration of a timer that starts after each sense phase when there are no pending page read operations.

Assignees

• Benisty Shay
• Sharifie Tal
• Baram Yair
• Sandisk Technologies Llc

Inventors

• Benisty Shay
• Sharifie Tal
• Baram Yair

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title