Detecting and sparing of optical PCIE cable channel attached IO drawer

Patent metadata

Field	Value
Publication number	US-9891998-B2
Application number	US-201514866931-A
Country	US
Kind code	B2
Filing date	Sep 26, 2015
Priority date	Nov 21, 2014
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A method, system and computer program product are provided for detecting state and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channels attached to an IO drawer. System firmware is provided for implementing health check functions and state detection and sparing functions. One or more optical cables are connected between a host bridge and an PCIE enclosure, each optical cable includes one or more spare optical channels. An identified failed optical channel is rerouted to the spare optical channel.

First claim

What is claimed is:

1. A method for detecting state and sparing of optical Peripheral Component Interconnect Express (PCI-Express or PCIE) cable channels attached to an IO drawer in a computer system, said computer system including a processor, a PCI host bridge (PHB); said PHB connected to said processor and a PCI link, said method comprising:
providing system firmware for implementing health check functions and detecting state and sparing functions;
providing at least one optical cable coupled between host bridge and an PCIE enclosure, each optical cable including at least one spare optical channel; and
identifying a failed optical channel and rerouting the failed optical channel to a spare optical channel using at least one PCIE lane transmit multiplexer and at least one PCIE lane receive multiplexer.

2. The method as recited in claim 1 , includes providing each optical cable with a plurality of optical channels for PCIE bidirectional traffic, at least one optical channel for sideband communications and the one or more spare optical channels.

3. The method as recited in claim 1 , includes providing lane sparing hardware on both ends of each optical cable.

4. The method as recited in claim 3 , includes providing lane sparing hardware with a set of PCIE lane multiplexers and a lane sparing hardware control device used to control the set of PCIE lane multiplexers.

5. The method as recited in claim 4 , includes programming the lane sparing hardware control device by system firmware for changing input to output mapping of the PCIE lane multiplexers.

6. The method as recited in claim 5 , includes controlling the lane sparing hardware control device using sideband signals and sideband structure including local field programmable gate array (FPGA) and remote FPGA on respective ends of each optical cable.

7. The method as recited in claim 1 , wherein system firmware performs a health check to detect when a PCIE link has degraded from its optimal lane width.

8. The method as recited in claim 1 , wherein system firmware performs a health check to detect a failed optical channel.

9. The method as recited in claim 1 , wherein system firmware interrogates PCIE and optical components of the optical path to detect a failed optical channel.

10. The method as recited in claim 1 , wherein providing at least one optical cable coupled between host bridge and an PCIE enclosure includes providing PCIE retimers, optical transmitters and optical receives coupled to said at least one optical cable, and wherein system firmware identifies a failed optical channel by interrogating a selected one of PCIE retimers, optical transmitters, and optical receivers.

11. The method as recited in claim 1 , wherein system firmware reroutes the optical path away from a faulted channel by programming routing multiplexers in the optical path hardware.

Assignees

• IBM

Inventors

• Arroyo Jesse P
• Bauman Ellen M
• Block Timothy R
• Engel Christopher J
• Naderi Kaveh
• Nordstrom Gregory M
• Pross Harald
• Sand Thomas R

Classifications

• G06F11/2012

  and using different communication protocols · CPC title

• G06F11/2007

  using redundant communication media · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/287

  Multiplexed DMA (G06F13/30 takes precedence) · CPC title

• G06F11/1423 Primary

  by reconfiguration of paths · CPC title