Selectively blocking branch prediction for a predetermined number of instructions

Patent metadata

Field	Value
Publication number	US-9891922-B2
Application number	US-201213524402-A
Country	US
Kind code	B2
Filing date	Jun 15, 2012
Priority date	Jun 15, 2012
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

Embodiments relate to selectively blocking branch instruction predictions. An aspect includes a computer system for performing selective branch prediction. The system includes memory and a processor, and the system is configured to perform a method. The method includes detecting a branch-prediction blocking instruction in a stream of instructions and blocking branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction.

First claim

What is claimed is:

1. A computer system for performing selective branch prediction, the computer system comprising:
memory configured to store instructions; and
a processor comprising:
an instruction fetch unit configured to fetch a stream of instructions from the memory;
an instruction decode unit configured to decode the stream of instructions;
an issue unit configured to issue the stream of instructions;
a plurality of execution units configured to execute the stream of instructions and a branch-prediction blocking instruction; and
a branch prediction circuit comprising:
a branch target buffer configured to store a plurality of branch target addresses associated with predicted branches;
a branch history circuit configured to store a plurality of patterns of taken and not-taken branch results for previously-resolved branch instructions, wherein the branch target buffer is separate from the branch history circuit; and

a branch prediction control circuit configured to turn on and off a branch prediction function of the branch prediction circuit based on a plurality of control signals provided from the execution units responsive to execution of the branch-prediction blocking instruction to block branch prediction operations of a predetermined number of branch instructions following the branch-prediction blocking instruction, wherein the branch prediction circuit prevents the instruction fetch unit from accessing the branch target buffer for the predetermined number of branch instructions following the branch-prediction blocking instruction and prevents the execution units from providing branch information of the predetermined number of branch instructions to the branch history circuit responsive to execution of the predetermined number of branch instructions by the execution units, and wherein the branch-prediction blocking instruction is generated and inserted into the stream of instructions by the branch prediction control circuit based on detecting a predetermined condition by the branch prediction circuit.

2. The computer system according to claim 1 , wherein the predetermined number is specified in the branch-prediction blocking instruction.

3. The computer system according to claim 1 , wherein the stream of instructions is a stream of instructions in a processing pipeline of the processor,
detecting the predetermined condition comprises determining that a fetched branch instruction corresponds to a predetermined type of branch instruction, and
inserting of the branch-prediction blocking instruction into the stream of instructions includes inserting the branch-prediction blocking instruction upstream from the fetched branch instruction.

4. The computer system according to claim 1 , wherein the predetermined condition is a characteristic of non-branch instructions in the stream of instructions.

5. The computer system according to claim 1 , wherein the predetermined number of branch instructions is greater than one.

6. A computer program product for performing selective branch prediction, the computer program product comprising:
a non-transitory storage medium readable by a processor, storing instructions for execution by the processor, wherein the processor comprises an instruction fetch unit configured to fetch a stream of instructions from a memory, an instruction decode unit configured to decode the stream of instructions, an issue unit configured to issue the stream of instructions, a plurality of execution units configured to execute the stream of instructions and a branch-prediction blocking instruction, and a branch prediction circuit comprising a branch prediction control circuit, wherein the execution of the instructions causes the processor to:
turn on and off, by the branch prediction control circuit, a branch prediction function of the branch prediction circuit based on a plurality of control signals provided from the execution units responsive to execution of the branch-prediction blocking instruction to block branch prediction operations of a predetermined number of branch instructions following the branch-prediction blocking instruction;
prevent, by the branch prediction control circuit, the instruction fetch unit from accessing a branch target buffer of the branch prediction circuit for the predetermined number of branch instructions following the branch-prediction blocking instruction, wherein the branch target buffer is configured to store a plurality of branch target addresses associated with predicted branches; and
prevent, by the branch prediction control circuit, the execution units from providing branch information of the predetermined number of branch instructions to a branch history circuit of the branch prediction circuit responsive to execution of the predetermined number of branch instructions by the execution units, wherein the branch history circuit is configured to store a plurality of patterns of taken and not-taken branch results for previously-resolved branch instructions, and the branch target buffer is separate from the branch history circuit, and wherein the branch-prediction blocking instruction is generated and inserted into the stream of instructions by the branch prediction control circuit based on detecting a predetermined condition by the branch prediction circuit.

7. The computer program product according to claim 6 , wherein the predetermined condition indicates that a fetched branch instruction corresponds to a predetermined type of branch instruction.

8. The computer program product according to claim 6 , wherein the predetermined number of branch instructions is greater than one.

9. The computer program product according to claim 6 , wherein the predetermined number is specified in the branch-prediction blocking instruction.

Assignees

• Bonanno James J
• Mayer Ulrich
• Saporito Anthony
• Shum Chung Lung K
• Slegel Timothy J
• IBM

Inventors

• Bonanno James J
• Mayer Ulrich
• Saporito Anthony
• Shum Chung Lung K
• Slegel Timothy J

Classifications

• G06F9/3844

  using dynamic branch prediction, e.g. using branch history tables · CPC title

• G06F9/30076 Primary

  to perform miscellaneous control operations, e.g. NOP · CPC title

• G06F9/3848

  using hybrid branch prediction, e.g. selection between prediction techniques · CPC title

• G06F9/38 Primary

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title