U-shaped vertical shunt resistor for Power Semiconductor module

Patent metadata

Field	Value
Publication number	US-9891247-B2
Application number	US-201414497437-A
Country	US
Kind code	B2
Filing date	Sep 26, 2014
Priority date	Sep 27, 2013
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A measurement resistor for current measurement is described. According to one exemplary embodiment, the measurement resistor includes a first and a second metal layer, an electrically insulating interlayer and a resistive layer. The first metal layer is arranged in a first plane. The second metal layer is arranged in a second plane that is essentially parallel to the first plane and separated from the first plane. The electrically insulating interlayer is arranged between the first and second metal layers and mechanically connects the first and second metal layers to one another. The resistive layer electrically connects the first and second metal layers to one another.

First claim

What is claimed is:

1. A measurement resistor, comprising:
a first metal layer arranged in a first plane;
a second metal layer arranged in a second plane that is parallel to the first plane and separated from the first plane;
an electrically insulating interlayer arranged between the first and second metal layers and which mechanically connects the first and second metal layers to one another; and
a resistive layer which electrically connects the first and second metal layers to one another,
wherein the first metal layer, the second metal layer, and the resistive layer form a U-shaped structure, wherein the U-shaped structure is configured to be placed on a planar surface with the first metal layer lying flush against the planar surface and physically supporting the measurement resistor and the second metal layer being vertically spaced apart from the first metal layer.

2. The measurement resistor of claim 1 , wherein a current flow direction through the resistive layer during operation extends substantially perpendicularly to the first and second planes.

3. The measurement resistor of claim 1 , wherein the metal layers consist of copper or a copper alloy, and/or wherein the interlayer consists of plastic or ceramic.

4. The measurement resistor of claim 1 , wherein the resistive layer consists of a resistive alloy that comprises at least two of the following metals: copper; manganese; tin; nickel; iron; chromium; and aluminum.

5. The measurement resistor of claim 1 , wherein the first and second metal layers are formed by metalizations of a DCB substrate, a DAB substrate or an AMB substrate, and wherein the resistive layer is arranged laterally on the substrate in such a way that the resistive layer electrically connects the metalizations of the substrate.

6. The measurement resistor of claim 1 , wherein the second metal layer extends along a side surface of the interlayer into the first plane, and wherein the first and second metal layers have, in the first plane, two contact surfaces electrically insulated from one another, which can be connected to corresponding contact surfaces of a substrate.

7. The measurement resistor of claim 1 , wherein the electrically insulating interlayer completely fills a central region of the U-shaped structure.

8. A method for producing a measurement resistor, the method comprising:
providing an approximately U-shaped structure, two approximately parallel branches of the U-shape structure forming two metal layers which are separated from one another and parallel to one another and which are electrically connected to one another by a resistive layer; and
arranging an interlayer made of insulating material between the parallel branches of the U-shape, so that the insulating material mechanically connects the two parallel branches of the U-shape,
wherein the U-shaped structure is configured to be placed on a planar surface with the first metal layer lying flush against the planar surface and physically supporting the measurement resistor and the second metal layer being vertically spaced apart from the first metal layer.

9. The method of claim 8 , further comprising:
injecting liquid plastic into the region between the parallel branches of the U-shape, so that the plastic mechanically connects the two parallel branches of the U-shape.

10. The method of claim 8 , further comprising:
pressing solid plastic or ceramic into the region between the parallel branches of the U-shape, so that the solid plastic or ceramic mechanically connects the two parallel branches of the U-shape.

11. The method of claim 8 , further comprising:
adhesive bonding solid plastic or ceramic into the region between the parallel branches of the U-shape, so that the solid plastic or ceramic mechanically connects the two parallel branches of the U-shape.

12. A method for producing a measurement resistor, the method comprising:
providing a power electronic substrate having an insulation carrier made of ceramic or insulated metal and metalization on both sides; and
fixing a resistive layer on a side surface of the power electronic substrate, so that the resistive layer connects the metalizations,
wherein the metalization on both sides and the resistive layer form a U-shaped structure, wherein the U-shaped structure is configured to be placed on a planar surface with a first one of the metalizations lying flush against the planar surface and physically supporting the measurement resistor and a second one of the metalizations being vertically spaced apart from the first metalization.

13. The method of claim 12 , wherein before fixing the resistive layer on a side surface of the power electronic substrate, this side surface is ground flat.

14. The method of claim 12 , wherein fixing the resistive layer on a side surface of the power electronic substrate is carried out by welding.

15. A power semiconductor module, comprising:
a power electronic substrate having a structured metalization, which comprises a plurality of contact pads;
at least one electronic component arranged on the power electronic substrate;
a measurement resistor, which comprises:
a first metal layer is arranged on one of the contact pads of the structured metalization and mechanically and electrically connected to that contact pad;
a second metal layer arranged in a plane parallel to the structured metalization and separated from the structured metallization;
an electrically insulating interlayer arranged between the first and second metal layers and which mechanically connects the first and second metal layers to one another; and
a resistive layer which electrically connects the first and second metal layers to one another,
wherein the first metal layer, the second metal layer, and the resistive layer form a U-shaped structure, wherein the U-shaped structure is configured to be placed on a planar surface with the first metal layer lying flush against the planar surface and physically supporting the measurement resistor and the second metal layer being vertically spaced apart from the first metal layer.

16. The power semiconductor module of claim 15 , further comprising:
a bond wire connected to the second metal layer by an ultrasonic bond connection so that the bond wire electrically contacts the measurement resistor.

Assignees

• Infineon Technologies Ag

Inventors

• Kanschat Peter
• Stolze Thilo

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W72/547

  Dispositions of multiple bond wires · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title