Power factor correction circuit and method for correcting power factor, converter device thereof

Patent metadata

Field	Value
Publication number	US-9887621-B2
Application number	US-201514983017-A
Country	US
Kind code	B2
Filing date	Dec 29, 2015
Priority date	Jan 22, 2015
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

The present examples relate to a power factor correction device, a power factor correction method, and a corresponding converter, in which when an input signal inputted into the converter is changed, a reference signal is also changed to fit to the input signal in consideration of only the frequency and the phase of the input signal. Thus, even without a specifically designated control circuit, examples make it possible to improve power factor correction and Total Harmonic Distortion (THD) and to reduce the size of a semiconductor chip, and examples are potentially used for a device receiving waveforms other than a sine wave.

First claim

What is claimed is:

1. A power factor correction circuit comprising:
a sensor configured to sense a sensing voltage on the basis of a value of a current flowing into a power switch that is configured to adjust an output voltage in accordance with an input voltage obtained by wave-rectifying an alternating current (AC) power; and
a power factor correction controller configured to receive a reference signal and the sensing voltage and to output a gate-on signal to turn on and to turn off the power switch, wherein the reference signal is generated by a reference signal generator configured to receive the sensing voltage and to generate a reference signal.

2. The power factor correction circuit of claim 1 , wherein the reference signal generator further comprises a detector configured to detect a turn-on time of the gate.

3. The power factor correction circuit of claim 2 , wherein the detector detects a first time and a second time that is a same gate-on time as the first time.

4. The power factor correction circuit of claim 3 , wherein the first time and the second time are symmetric to each other.

5. The power factor correction circuit of claim 1 , wherein the reference signal generator samples a peak signal of the sensing voltage, in response to a first time being detected.

6. The power factor correction circuit of claim 5 , wherein the peak signal of the sensing voltage that is sampled is maintained until a second time is detected.

7. The power factor correction circuit of claim 6 , wherein the second time is a same duration as the first time.

8. The power factor correction circuit of claim 1 , wherein the reference signal generator samples and holds the sensing voltage during a first gate-on maintaining time and a second gate-on maintaining time that is symmetric to the first gate-on maintaining time.

9. A converter comprising:
a reference signal generator configured to receive a sensing voltage of a power switch and to generate a reference signal; and
a power factor correction controller configured to receive the reference signal and the sensing voltage and to generate and output a gate-on signal for the power switch,
wherein the reference signal generator generates the reference signal while maintaining a peak signal of the sensing voltage during a first time in which a gate turn-on period of the power switch is set to a desired time and a second turn-on time that is the same as the first time are detected.

10. A power factor correction method comprising:
checking a sensing voltage according to an input voltage by means of a power factor correction circuit;
detecting a first time while the sensing voltage is checked;
sampling the sensing voltage in response to the first time being detected; and
maintaining the sensing voltage until a second time the same as the first time is detected.

11. The method of claim 10 , wherein the first time and the second time are gate turn-on maintaining times for the power switch and have a same length.

12. The method of claim 11 , wherein the sensing voltage increases until the first time is detected, and the sensing voltage decreases after the second time is detected.

13. The method of claim 12 , wherein the gate turn-on maintaining time decreases when the sensing voltage increases, and the gate turn-on maintaining time increases when the sensing voltage decreases.

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Cui zhi yuan
• Hwang In Ho
• Ryu Young Gi
• Jeong Sang Hoon
• Lim Gyu Ho

Classifications

• Y02B70/126

  Cross-Sectional Technologies · mapped topic

• H02M1/4225 Primary

  using a non-isolated boost converter · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

• H02M1/42 Primary

  Circuits or arrangements for compensating for or adjusting power factor in converters or inverters · CPC title

• G05F1/70

  Regulating power factor; Regulating reactive current or power · CPC title