Laser processing of superconductor layers

Patent metadata

Field	Value
Publication number	US-9887342-B2
Application number	US-201715415071-A
Country	US
Kind code	B2
Filing date	Jan 25, 2017
Priority date	Nov 27, 2013
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

A method of forming a superconductor includes exposing a layer disposed on a substrate to an oxygen ambient, and selectively annealing a portion of the layer to form a superconducting region within the layer.

First claim

What is claimed is:

1. An integrated superconductor device, comprising:
a substrate base;
a buffer layer disposed on the substrate base and comprising a preferred crystallographic orientation; and
a superconductor layer disposed on the buffer layer, the superconductor layer comprising a superconducting region, and a first region outside the superconducting region, wherein the first region and superconducting region have at least three elements in common, wherein the superconducting region comprises a superconductor material having a preferred crystallographic orientation in which the c-axis of crystallites are arranged perpendicularly to the plane of the substrate in preference over other possible orientations, and
wherein the first region comprises an amorphous material, a poorly crystalline material, randomly oriented crystallites, or an a-axis orientation.

2. The integrated superconductor device of claim 1 , wherein the superconducting region comprises a copper oxide-based superconductor material having a c-axis texture in which the crystallites of the superconducting region have their c-axes oriented perpendicularly to a plane of the substrate.

3. The integrated superconductor device of claim 1 , wherein the superconducting region has a critical current greater than 2 MA/cm 2 .

4. An integrated superconductor device, comprising:
a substrate comprising a substrate base, the substrate defining a plane of the substrate;
a buffer layer disposed on the substrate base; and
a superconductor layer disposed on the buffer layer, the superconductor layer comprising a superconducting region, and a first region, disposed outside the superconducting region,
wherein the superconducting region comprises superconductor material having a preferred crystallographic orientation in which the c-axis of crystallites are arranged perpendicularly to the plane of the substrate in preference over other possible orientations, and
wherein the first region does not comprise a superconductor material having the preferred crystallographic orientation in which the c-axis of crystallites are arranged perpendicularly to the plane of the substrate in preference over other possible orientations.

5. The integrated superconductor device of claim 4 , wherein the superconducting region has higher critical current than the first region.

6. The integrated superconductor device of claim 4 , wherein the superconducting region and the first region have at least three elements in common.

7. The integrated superconductor device of claim 4 , wherein the superconducting region and the first region have different crystalline orientations.

8. The integrated superconductor device of claim 4 , wherein the superconducting region comprises a serpentine shape, a spiral shape, or a plurality of lines.

9. The integrated superconductor device of claim 4 , wherein the first region comprises amorphous material or randomly oriented polycrystalline superconductor crystallites.

10. The integrated superconductor device of claim 4 , wherein the superconductor layer comprises ReBa 2 Cu 3 O 7−x where Re is a rare earth element, wherein the first region comprises a set of regions in which crystallites of the superconductor layer have their c-axes oriented parallel to the plane of the substrate.

11. The integrated superconductor device of claim 4 , wherein the substrate comprises a set of raised features having sidewalls, and wherein the superconductor layer comprises superconductor material disposed on the sidewalls.

12. The integrated superconductor device of claim 4 ,
wherein the buffer layer comprising a preferred crystallographic orientation that is operative to generate, in the superconductor layer, superconductor material having the preferred crystallographic orientation in which the c-axis of crystallites are arranged perpendicularly to the plane of the substrate in preference over other possible orientations.

13. The integrated superconductor device of claim 4 , wherein the substrate base comprises a silicon-on-insulator (SOI) substrate, wherein a silicon layer of the SOI substrate comprises a thickness less than 10 micrometers.

14. An integrated superconductor substrate, comprising:
a substrate defining a plane of the substrate, the substrate further comprising a substrate base, wherein the substrate base comprises a set of raised features having sidewalls;
a buffer layer disposed on the substrate base; and
a superconductor layer disposed on the buffer layer, the superconductor layer comprising:
a superconducting region including superconductor material disposed on the sidewalls; and
a first region, disposed outside the superconducting region,
wherein the superconducting region comprises superconductor material having a c-axis orientation in which the c-axes of the crystallites are aligned perpendicularly to the plane of the substrate, and
wherein the first region does not comprise a superconductor material having the c-axis orientation.

15. The integrated superconductor substrate of claim 14 , further comprising:
a metal disposed on a portion of the superconductor layer, including the superconductor material disposed on the sidewalls.

16. The integrated superconductor substrate of claim 14 , wherein the superconductor layer comprises a material in a family of ReBa 2 Cu 3 O 7−x material, wherein Re is a rare earth element, and wherein the first region comprises a set of regions in which crystallites of the layer have their c-axes oriented parallel to the plane of the substrate.

17. The integrated superconductor substrate of claim 14 ,
the first region comprising a poorly crystalline or amorphous region having a thickness greater than two micrometers.

18. The integrated superconductor device of claim 14 ,
wherein the buffer layer comprising a preferred crystallographic orientation that is operative to generate, in the superconductor layer, superconductor material having the c-axis orientation in which the c-axes of the crystallites are aligned perpendicularly to the plane of the substrate.

Assignees

• Varian Semiconductor Equipment Ass Inc

Inventors

• Wang Connie P
• Murphy Paul
• Sullivan Paul
• Chatterjee Sukti

Classifications

• Y10T428/24174

  including sheet or component perpendicular to plane of web or sheet · CPC title

• H01L39/128 Primary

  Electricity · mapped topic

• H01L39/249

  Electricity · mapped topic

• H01L39/2464

  Electricity · mapped topic

• H10N60/0884

  Treatment of superconductor layers by irradiation, e.g. ion-beam, electron-beam, laser beam or X-rays · CPC title