Normally-off field effect transistor

Patent metadata

Field	Value
Publication number	US-9887267-B2
Application number	US-201615234350-A
Country	US
Kind code	B2
Filing date	Aug 11, 2016
Priority date	Aug 11, 2015
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

A normally-off transistor with a high operating voltage is provided. The transistor can include a barrier above the channel and an additional barrier layer located below the channel. A source electrode and a drain electrode are connected to the channel and a gate electrode is connected to the additional barrier layer located below the channel. The bandgap for each of the barrier layers can be larger than the bandgap for the channel. A polarization charge induced at the interface between the additional barrier layer below the channel and the channel depletes the channel. A voltage can be applied to the bottom barrier to induce free carriers into the channel and turn the channel on.

First claim

What is claimed is:

1. A field effect transistor comprising:
a first barrier and a second barrier;
a channel located between the first barrier and the second barrier, wherein a bandgap for each of the first barrier and the second barrier is larger than a bandgap for the channel, wherein a doping type for the first barrier is opposite to a doping type for the channel;
a source electrode and a drain electrode connected to the channel; and
a gate electrode connected to the first barrier.

2. The transistor of claim 1 , wherein the first barrier is doped with p-type dopants and the channel is doped with n-type dopants.

3. The transistor of claim 1 , wherein at least one of: the first barrier, the second barrier, or the channel are formed by short-period superlattices.

4. The transistor of claim 1 , wherein the source electrode and drain electrode form a multifinger pattern.

5. The transistor of claim 1 , further comprising a set of field-plate electrodes directly connected or capacitively coupled to at least one of: the source, drain, and gate electrodes.

6. The transistor of claim 1 , further comprising a passivation layer located above the second barrier.

7. The transistor of claim 6 , further comprising a charge control electrode connecting at least one of: the passivation layer or the second barrier to the channel.

8. The transistor of claim 6 , further comprising at least one additional gate electrode connected to at least one of: the passivation layer or the second barrier.

9. The transistor of claim 6 , further comprising a charge control electrode connecting the gate electrode to at least one of: the passivation layer or the second barrier.

10. The transistor of claim 9 , wherein the charge control electrode capacitively couples the gate electrode, the passivation layer, and the second barrier.

11. A field effect transistor comprising:
a first barrier and a second barrier;
a channel located between the first barrier and the second barrier, wherein a bandgap for each of the first barrier and the second barrier is larger than a bandgap for the channel, and wherein a doping type for the first barrier is opposite to a doping type for the channel and the doping type for the channel is a same doping type as a doping type for the second barrier;
a source electrode and a drain electrode connected to the channel; and
a gate electrode connected to the first barrier.

12. The transistor of claim 11 , wherein the first barrier is doped with p-type dopants and the channel is doped with n-type dopants.

13. The transistor of claim 11 , wherein the source electrode and the drain electrode form a multifinger pattern.

14. The transistor of claim 11 , at least one of: the first barrier, the second barrier, or the channel, is formed by a short-period superlattice.

15. The transistor of claim 11 , further comprising a passivation layer located above the second barrier.

16. The transistor of claim 15 , further comprising a charge control electrode connecting the gate electrode to at least one of: the passivation layer or the second barrier.

17. The transistor of claim 15 , further comprising a charge control electrode connecting at least one of: the passivation layer or the second barrier to the channel.

18. The transistor of claim 15 , further comprising at least one additional gate electrode connected to at least one of: the passivation layer or the second barrier.

19. A field effect transistor comprising:
a first barrier and a second barrier;
a channel located between the first barrier and the second barrier, wherein a bandgap for each of the first barrier and the second barrier is larger than a bandgap for the channel;
a passivation layer located above the second barrier;
a source electrode and a drain electrode connected to the channel;
a gate electrode connected to the first barrier, wherein the gate electrode is located on a portion of the first barrier outside of a region defined by the source electrode and the drain electrode; and
a charge control electrode connecting the gate electrode to at least one of: the passivation layer or the second barrier.

20. The transistor of claim 19 , wherein a doping type for the first barrier is opposite to a doping type for the channel.

Assignees

• Sensor Electronic Tech Inc

Inventors

• Simin Grigory
• Shur Michael

Classifications

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H01L29/423

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic