Memory arrays

Patent metadata

Field	Value
Publication number	US-9887239-B2
Application number	US-201715639423-A
Country	US
Kind code	B2
Filing date	Jun 30, 2017
Priority date	Jun 7, 2010
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F 2 .

First claim

I claim:

1. A memory array comprising:
a plurality of memory cell units; and
planar areas of the individual memory cell units being about 2F 2 wherein F represents minimum feature size.

2. The memory array of claim 1 wherein the memory cell units comprise a rectangular perimeter having two sides that are of dimension 2F and two sides that are of dimension F.

3. The memory array of claim 1 wherein the memory cell units comprise phase change material.

4. The memory array of claim 3 wherein the phase change material comprises chalcogenides.

5. The memory array of claim 3 wherein the phase change material comprises alloys of germanium, antimony and tellurium.

6. The memory array of claim 1 wherein the plurality of memory cell units comprises access devices other than transistors.

7. The memory array of claim 1 wherein the plurality of memory cell units comprises access devices, the access devices comprising at least one of diodes and ovonic threshold switches.

8. The memory array of claim 1 wherein the plurality of memory cell units comprises access devices, the access devices comprising a single homogeneous composition.

9. The memory array of claim 1 wherein the plurality of memory cell units comprises access devices, the access devices comprising multiple discrete compositions.

10. The memory array of claim 1 wherein each memory cell unit comprises a single access device.

11. The memory array of claim 1 wherein each memory cell unit comprises multiple access devices.

12. The memory array of claim 1 wherein the memory cell units comprise memory cell material.

13. The memory array of claim 12 wherein the memory cell material comprises a single homogeneous composition.

14. The memory array of claim 12 wherein the memory cell material comprises multiple discrete compositions.

15. The memory array of claim 12 wherein the memory cell material is directly adjacent bitlines.

16. The memory array of claim 12 wherein the memory cell material is directly adjacent wordlines.

17. The memory array of claim 15 wherein the memory cell material surrounds an entire periphery of at least a portion of at least one of the bitlines.

18. The memory array of claim 15 wherein the memory cell material is discontinuous around a periphery of at least a portion of at least one of the bitlines.

Assignees

• Micron Technology Inc

Inventors

• Liu Zengtao T

Classifications

• G11C2213/18

  Memory cell being a nanowire having RADIAL composition · CPC title

• G11C5/025 Primary

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C7/1087

  Data input latches · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title