Method for manufacturing thin film transistor and related active layer for thin film transistor, thin film transistor, array substrate, and display apparatus

US9887213B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9887213-B2
Application numberUS-201515125786-A
CountryUS
Kind codeB2
Filing dateAug 14, 2015
Priority dateDec 23, 2014
Publication dateFeb 6, 2018
Grant dateFeb 6, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure provides a method for forming an active layer with a pattern. The method includes forming an amorphous silicon layer and forming a function layer on the amorphous silicon layer. The function layer has a same pattern as the active layer. The method further includes performing a crystallization process for converting the amorphous silicon layer to a poly-silicon layer. The poly-silicon layer has first portions covered by the function layer and second portions not covered by the function layer, and grain sizes of the poly-silicon in the first portions are larger than grain sizes of the poly-silicon in the second portions.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for forming an active layer with a pattern, comprising: forming an amorphous silicon layer; forming a patterned function layer on the amorphous silicon layer, wherein the patterned function layer has a same pattern as the active layer; and performing, after forming the patterned function layer, a crystallizing process for converting the amorphous silicon layer to a poly-silicon layer, wherein the poly-silicon layer has first portions covered by the patterned function layer and second portions not covered by the patterned function layer, and grain sizes of the poly-silicon in the first portions are larger than grain sizes of the poly-silicon in the second portions. 2. The method according to claim 1 , wherein the patterned function layer is made of a non-metal material including silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride. 3. The method according to claim 1 , wherein a thickness of the patterned function layer is about 5 to about 20 nm. 4. The method according to claim 1 , further comprising: applying a mask for patterning the active layer and patterning a function film to form the patterned function layer with the same pattern as the active layer. 5. The method according to claim 1 , wherein crystallizing process includes applying an excimer laser annealing process. 6. The method according to claim 1 , further including: forming a buffer layer on a substrate, wherein the buffer layer is made of silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride. 7. The method according to claim 6 , wherein the substrate is made of glass. 8. The method according to claim 1 , wherein the amorphous silicon layer and the patterned function layer are formed consecutively by plasma enhanced chemical vapor deposition. 9. The method according to claim 1 , wherein the heat retaining duration for the first portions of the amorphous silicon layer covered by the patterned function layer is longer than or equal to 35 ns. 10. The method according to claim 1 , wherein the grain sizes of the poly-silicon formed in the first portions covered by the patterned function layer are about 0.3 to 0.5 μm. 11. The method according to claim 1 , further comprising: removing the patterned function layer after crystallizing the amorphous silicon layer and before patterning the poly-silicon layer. 12. The method according to claim 11 , wherein removing the patterned function layer includes applying an etching process to remove the patterned function layer.

Assignees

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Classifications

  • using laser beams · CPC title

  • Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit (G02F1/135 takes precedence) · CPC title

  • Thermal treatments, e.g. annealing or sintering · CPC title

  • with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

  • Electricity · mapped topic

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What does patent US9887213B2 cover?
The present disclosure provides a method for forming an active layer with a pattern. The method includes forming an amorphous silicon layer and forming a function layer on the amorphous silicon layer. The function layer has a same pattern as the active layer. The method further includes performing a crystallization process for converting the amorphous silicon layer to a poly-silicon layer. The …
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01L27/1222. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 06 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).