Display device
US-12125855-B2 · Oct 22, 2024 · US
US9887213B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9887213-B2 |
| Application number | US-201515125786-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 14, 2015 |
| Priority date | Dec 23, 2014 |
| Publication date | Feb 6, 2018 |
| Grant date | Feb 6, 2018 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
The present disclosure provides a method for forming an active layer with a pattern. The method includes forming an amorphous silicon layer and forming a function layer on the amorphous silicon layer. The function layer has a same pattern as the active layer. The method further includes performing a crystallization process for converting the amorphous silicon layer to a poly-silicon layer. The poly-silicon layer has first portions covered by the function layer and second portions not covered by the function layer, and grain sizes of the poly-silicon in the first portions are larger than grain sizes of the poly-silicon in the second portions.
Opening claim text (preview).
What is claimed is: 1. A method for forming an active layer with a pattern, comprising: forming an amorphous silicon layer; forming a patterned function layer on the amorphous silicon layer, wherein the patterned function layer has a same pattern as the active layer; and performing, after forming the patterned function layer, a crystallizing process for converting the amorphous silicon layer to a poly-silicon layer, wherein the poly-silicon layer has first portions covered by the patterned function layer and second portions not covered by the patterned function layer, and grain sizes of the poly-silicon in the first portions are larger than grain sizes of the poly-silicon in the second portions. 2. The method according to claim 1 , wherein the patterned function layer is made of a non-metal material including silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride. 3. The method according to claim 1 , wherein a thickness of the patterned function layer is about 5 to about 20 nm. 4. The method according to claim 1 , further comprising: applying a mask for patterning the active layer and patterning a function film to form the patterned function layer with the same pattern as the active layer. 5. The method according to claim 1 , wherein crystallizing process includes applying an excimer laser annealing process. 6. The method according to claim 1 , further including: forming a buffer layer on a substrate, wherein the buffer layer is made of silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride. 7. The method according to claim 6 , wherein the substrate is made of glass. 8. The method according to claim 1 , wherein the amorphous silicon layer and the patterned function layer are formed consecutively by plasma enhanced chemical vapor deposition. 9. The method according to claim 1 , wherein the heat retaining duration for the first portions of the amorphous silicon layer covered by the patterned function layer is longer than or equal to 35 ns. 10. The method according to claim 1 , wherein the grain sizes of the poly-silicon formed in the first portions covered by the patterned function layer are about 0.3 to 0.5 μm. 11. The method according to claim 1 , further comprising: removing the patterned function layer after crystallizing the amorphous silicon layer and before patterning the poly-silicon layer. 12. The method according to claim 11 , wherein removing the patterned function layer includes applying an etching process to remove the patterned function layer.
using laser beams · CPC title
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit (G02F1/135 takes precedence) · CPC title
Thermal treatments, e.g. annealing or sintering · CPC title
with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title
Electricity · mapped topic
Related publications grouped by family.
Answers are generated from the same data shown on this page.