Semiconductor devices including a peripheral circuit region and first and second memory regions, and related programming methods

Patent metadata

Field	Value
Publication number	US-9887199-B2
Application number	US-201514670667-A
Country	US
Kind code	B2
Filing date	Mar 27, 2015
Priority date	May 21, 2014
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

Semiconductor devices are provided. A semiconductor device includes a peripheral circuit region and a first memory region that are side by side on a substrate. Moreover, the semiconductor device includes a second memory region that is on the peripheral circuit region and the first memory region. Related methods of programming semiconductor devices are also provided.

First claim

What is claimed is:

1. A semiconductor device comprising:
a peripheral circuit part and a first memory part side by side on a substrate; and
a second memory part on the peripheral circuit part and the first memory part,
wherein the second memory part comprises:
a semiconductor layer on the peripheral circuit part and the first memory part;
active pillars protruding from the semiconductor layer;
word lines adjacent sidewalls of the active pillars; and
bit lines on the active pillars, and

wherein the peripheral circuit part extends under the active pillars so that the peripheral circuit part is between the active pillars and the substrate and so that the active pillars overlap the peripheral circuit part,
wherein the first memory part comprises: first word lines that are parallel to each other and are equidistant from a surface of the substrate, each of the first word lines connected to respective first memory cells,
wherein the second memory part comprises: second word lines, comprising the word lines that are adjacent the sidewalls of the active pillars, that are parallel to each other and are at different respective distances from the surface of the substrate, and
wherein the first memory part further comprises a bit line that extends under the semiconductor layer of the second memory part so that the semiconductor layer of the second memory part overlaps a portion of the bit line of the first memory part.

2. The semiconductor device of claim 1 , wherein the first memory part comprises:
a gate electrode on the substrate; and
a tunnel dielectric layer, a data storage element, and a blocking dielectric layer sequentially stacked between the substrate and the gate electrode.

3. The semiconductor device of claim 1 , wherein the first memory part is configured to be used as a buffer memory.

4. The semiconductor device of claim 1 , wherein the first memory part comprises a memory structure of at least one of a static random access memory (SRAM), a dynamic random access memory (DRAM), a magnetic random access memory (MRAM), a phase change random access memory (PRAM), a ferroelectric random access memory (FRAM), a resistive random access memory (RRAM), a NOR flash memory, or a NAND flash memory.

5. The semiconductor device of claim 1 , wherein the first memory part is adjacent one or more sides of the peripheral circuit part on the substrate.

6. The semiconductor device of claim 1 ,
wherein the first memory part comprises a first plurality of memory cells including the respective first memory cells,
wherein the second memory part comprises a second plurality of memory cells,
wherein a first quantity of the first plurality of memory cells is smaller than a second quantity of the second plurality of memory cells,
wherein each of the first plurality of memory cells is configured to store one-bit data, and
wherein each of the second plurality of memory cells is configured to provide eight states.

7. The semiconductor device of claim 1 ,
wherein the peripheral circuit part comprises a peripheral gate electrode,
wherein the first memory part comprises a cell gate electrode, and
wherein a first width of the peripheral gate electrode is wider than a second width of the cell gate electrode.

8. The semiconductor device of claim 1 , wherein the first memory part and the second memory part constitute a main memory.

9. The semiconductor device of claim 1 ,
wherein the first memory part comprises a volatile memory structure, and
wherein the second memory part comprises a non-volatile memory structure.

10. The semiconductor device of claim 1 ,
wherein at least one of the word lines comprises a first portion overlapping the peripheral circuit part and a second portion overlapping the first memory part, and
wherein the first portion is longer than the second portion.

Assignees

• Lim Joon Sung
• Yun Jang Gn
• Cho Hoosung
• Samsung Electronics Co Ltd

Inventors

• Lim Joon Sung
• Yun Jang Gn
• Cho Hoosung

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C11/56

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title