Conductive structure having an entrenched high resistive layer

Patent metadata

Field	Value
Publication number	US-9887158-B1
Application number	US-201615340982-A
Country	US
Kind code	B1
Filing date	Nov 2, 2016
Priority date	Oct 4, 2016
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

A conductive structure includes a substrate including a first dielectric layer formed thereon, a first trench formed in the first dielectric layer, a first barrier layer formed in the first trench, a first nucleation layer formed on the first barrier layer, a first metal layer formed on the first nucleation layer, and a first high resistive layer sandwiched in between the first barrier layer and the first metal layer.

First claim

What is claimed is:

1. A conductive structure comprising:
a substrate comprising a first dielectric layer formed thereon;
a first trench formed in the first dielectric layer;
a first barrier layer formed in the first trench;
a first nucleation layer formed on the first barrier layer;
a first metal layer formed on the first nucleation layer; and
a first high resistive layer sandwiched in between a portion of the first barrier layer and a portion of the first metal layer.

2. The conductive structure according to claim 1 , wherein a bottom of the first metal layer contacts the first nucleation layer.

3. The conductive structure according to claim 1 , further comprising a second nucleation layer sandwiched in between the first high resistive layer and the first metal layer, and a bottom of the first metal layer contacting the second nucleation layer.

4. The conductive structure according to claim 1 , wherein the first metal layer comprises a metal material, and the first high resistive layer comprises a metal nitride, a metal oxide, or a metal carbide of the metal material of the first metal layer.

5. The conductive structure according to claim 4 , wherein the metal material of the first metal layer comprises tungsten (W), and the first high resistive layer comprises tungsten nitride (WN), tungsten oxide (WO), or tungsten carbide (WC).

6. The conductive structure according to claim 1 , further comprising:
at least a source/drain region formed in the substrate; and
a spacer formed in the first dielectric layer, and the first trench being defined by the spacer.

7. The conductive structure according to claim 6 , further comprising at least a high-k gate dielectric layer and a work function metal layer, and the high-k gate dielectric layer and the work function metal layer being sandwiched in between the first barrier layer and the substrate.

8. The conductive structure according to claim 1 , further comprising:
at least transistor device formed on the substrate and embedded in the first dielectric layer; and
a second dielectric layer formed on the transistor device and the first dielectric layer.

9. The conductive structure according to claim 8 , wherein the first trench is formed in the first dielectric layer and the second dielectric layer, and a top surface of the first metal layer, a top surface of the first high resistive layer, a top surface of the first nucleation layer, and a top surface of the second dielectric layer are coplanar.

10. The conductive structure according to claim 8 , wherein the first trench is formed in the first dielectric layer, and a top surface of the first metal layer, a top surface of the first high resistive layer, a top surface of the first nucleation layer, and a top surface of the first dielectric layer are coplanar.

11. The conductive structure according to claim 10 , further comprising:
a second trench formed in the second dielectric layer;
a second barrier layer formed in the second trench;
a third nucleation layer formed on the second barrier layer;
a second metal layer formed on the second barrier layer in the second trench; and
a second high resistive layer sandwiched in between the second barrier layer and the second metal layer.

Assignees

• United Microelectronics Corp

Inventors

• Li Kun Ju
• Hung Kuo Chin
• Tsai Min Chuan
• Tsai Wei Chuan
• Liao Yi Han
• Lu Chun Tsen
• Tsai Fu Shou
• Hsu Li Chieh

Classifications

• H10W20/0425

  comprising multiple stacked seed or nucleation layers · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title