Semiconductor devices, FinFET devices, and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9887136-B2
Application number	US-201715473627-A
Country	US
Kind code	B2
Filing date	Mar 30, 2017
Priority date	Mar 7, 2016
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

Semiconductor devices and FinFET devices are disclosed. A substrate has first and second regions. First and second gates are on the substrate in the first region, and a first end sidewall of the first gate is faced to a second end sidewall of the second gate. Third and fourth gates are on the substrate in the second region, and a third end sidewall of the third gate is faced to a fourth end sidewall of the fourth gate. A dielectric layer is between the first and second gates and between the third and fourth gates. The first and second regions have different pattern densities, and an included angle between the substrate and a sidewall of the dielectric layer between the first and second gates is different from an included angle between the substrate and a sidewall of the dielectric layer between the third and fourth gates.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having a first region and a second region;
a first gate and a second gate on the substrate in the first region, wherein a first end sidewall of the first gate is faced to a second end sidewall of the second gate;
a third gate and a fourth gate on the substrate in the second region, wherein a third end sidewall of the third gate is faced to a fourth end sidewall of the fourth gate; and
a dielectric layer between the first end sidewall of the first gate and the second end sidewall of the second gate and between the third end sidewall of the third gate and the fourth end sidewall of the fourth gate,
wherein a pattern density of the first region is different from a pattern density of the second region, and an included angle between the substrate and a sidewall of the dielectric layer between the first gate and the second gate is different from an included angle between the substrate and a sidewall of the dielectric layer between the third gate and the fourth gate.

2. The semiconductor device of claim 1 , wherein the pattern density of the first region is less than the pattern density of the second region, and the included angle between the substrate and the sidewall of the dielectric layer between the first gate and the second gate is greater than the included angle between the substrate and the sidewall of the dielectric layer between the third gate and the fourth gate.

3. The semiconductor device of claim 2 , wherein the included angle between the substrate and the sidewall of the dielectric layer between the first gate and the second gate is greater than 90 degrees, and the included angle between the substrate and the sidewall of the dielectric layer between the third gate and the fourth gate is from 85 to 95 degrees.

4. The semiconductor device of claim 1 , wherein the first region is a periphery region, and the second region is a core region.

5. The semiconductor device of claim 1 , wherein a distance from the first end sidewall of the first gate to the second end sidewall of the second gate is greater than a distance from the third end sidewall of the third gate to the fourth end sidewall of the fourth gate.

6. The semiconductor device of claim 1 , wherein a top surface of the dielectric layer is substantially level with top surfaces of the first gate to fourth gates.

7. The semiconductor device of claim 1 , further comprising a void in at least one of a part of the dielectric layer between the first end sidewall of the first gate and the second end sidewall of the second gate and another part of the dielectric layer between the third end sidewall of the third gate and the fourth end sidewall of the fourth gate.

8. The semiconductor device of claim 1 , wherein the substrate has at least one first fin and at least one second fin in the first region and has at least one third fin and at least one fourth fin in the second region, and wherein the first gate is across the at least one first fin and the second gate is across the at least one second fin, and the third gate is across the at least one third fin and the fourth gate is across the at least one fourth fin.

9. A FinFET device, comprising:
a substrate having at least one first fin and at least one second fin in a first region and having at least one third fin and at least one fourth fin in a second region;
a first gate across the at least one first fin and a second gate across the at least one second fin, wherein a first end sidewall of the first gate is faced to a second end sidewall of the second gate;
a third gate across the at least one third fin and a fourth gate across the at least one fourth fin, wherein a third end sidewall of the third gate is faced to a fourth end sidewall of the fourth gate; and
a dielectric layer between the first end sidewall of the first gate and the second end sidewall of the second gate and between the third end sidewall of the third gate and the fourth end sidewall of the fourth gate,
wherein a distance from the first end sidewall of the first gate to a sidewall of the at least one first fin is at least two times a distance from the third end sidewall of the third gate to a sidewall of the at least one third fin, and the dielectric layer between the first end sidewall of the first gate and the second end sidewall of the second gate has a cross-sectional profile different from that of the dielectric layer between the third end sidewall of the third gate and the fourth end sidewall of the fourth gate.

10. The FinFET device of claim 9 , wherein the dielectric layer between the first end sidewall of the first gate and the second end sidewall of the second gate has a wide top and narrow bottom profile.

11. The FinFET device of claim 9 , wherein a distance from the second end sidewall of the second gate to a sidewall of the at least one second fin is at least two times a distance from the fourth end sidewall of the fourth gate to a sidewall of the at least one fourth fin.

12. The FinFET device of claim 9 , wherein an included angle between the substrate and a sidewall of the dielectric layer between the first gate and the second gate is different from an included angle between the substrate and a sidewall of the dielectric layer between the third gate and the fourth gate.

13. The FinFET device of claim 9 , wherein the first region is a periphery region, and the second region is a core region.

14. The FinFET device of claim 9 , wherein a distance from the first end sidewall of the first gate to the second end sidewall of the second gate is greater than a distance from the third end sidewall of the third gate to the fourth end sidewall of the fourth gate.

15. The FinFET device of claim 9 , wherein a top surface of the dielectric layer is substantially level with top surfaces of the first gate to fourth gates.

16. A method of forming a FinFET device, comprising:
providing a substrate with at least one first fin and at least one second fin in a first region and at least one third fin and at least one fourth fin in a second region;
forming a first dummy strip across the at least one first fin and the at least one second fin in the first region and forming a second dummy strip across the at least one third fin and the at least one fourth fin in the second region;
performing an end cut process to the first and second dummy strips, so as to form a first opening through the first dummy strip and a second opening through the second dummy strip, wherein a cross-sectional profile of the first opening is different from a cross-sectional profile of the second opening; and
forming a dielectric layer in the first opening and the second opening.

17. The method of claim 16 , wherein an included angle between a sidewall of the first opening and the substrate is different from an included angle between a sidewall of the second opening and the substrate.

18. The method of claim 17 , wherein a pattern density of the first region is less than a pattern density of the second region, and the included angle between the sidewall of the first opening and the substrate is greater than the included angle between the sidewall of the second opening and the substrate.

19. The method of claim 16 , wherein the end cut process comprises:
forming a mask layer on the substrate, wherein the mask layer exposes a portion of the first dummy strip and a portion of the second dummy strip; and
removing the portion of the first dummy strip and the portion of the second dummy strip by using the mask layer as an etch mask.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Che Cheng
• Lin Chih Han
• Tseng Horng Huei

Classifications

• H10D84/83138

  the IGFETs characterised by having different shapes or dimensions of their gate conductors · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H01L21/823456 Primary

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic