Write voltage generation circuit and memory apparatus

Patent metadata

Field	Value
Publication number	US-9887012-B2
Application number	US-201615142988-A
Country	US
Kind code	B2
Filing date	Apr 29, 2016
Priority date	May 1, 2015
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

A write voltage generation circuit includes: a power supply terminal that receives an external power supply voltage; a boosting circuit that boosts the external power supply voltage to generate a boosted voltage; and a selector that selects either one of the external power supply voltage and the boosted voltage, and outputs the selected voltage as the write voltage. The selector selects the external power supply voltage as the write voltage in a first part of a write period for writing data to a memory cell, and selects the boosted voltage as the write voltage in a latter part of the write period.

First claim

What is claimed is:

1. A write voltage generation and application circuit for generating a write voltage and applying the write voltage to a memory cell thereby causing said memory cell to memorize data, the write voltage generation and application circuit comprising:
a power supply terminal configured to receive an external power supply voltage;
a boosting circuit configured to boost said external power supply voltage to generate a boosted supply voltage; and
a selective relay circuit configured
to selectively relay said external power supply voltage as said write voltage to said memory cell so that a first charge is stored in said memory cell during a first part of a write period for writing data to said memory cell, and
to selectively relay said boosted supply voltage as said write voltage to said memory cell so that a second charge is stored in said memory cell during a latter part of said write period,

the stored first charge being greater in amount than the stored second charge.

2. The write voltage generation circuit according to claim 1 , comprising a counter configured to receive a write signal including a pulse series indicating timing to apply said write voltage to said memory cell in said write period, and to count the number of pulses in said write signal to obtain a count value, wherein
said selective relay circuit selectively relays said external power supply voltage to said memory cell between a start of said write period and when the count value reaches a predetermined number, and selectively relays said boosted supply voltage as said write voltage to said memory cell after the count value reaches the predetermined number.

3. The write voltage generation circuit according to claim 2 , comprising a voltage controlled oscillator configured to generate an oscillation signal including a pulse series having a frequency corresponding to a voltage value of said external power supply voltage, the oscillation signal being generated as said write signal.

4. A memory apparatus for writing data by applying a write voltage to a memory cell thereby causing said memory cell to memorize data, the memory apparatus comprising:
a power supply terminal configured to receive an external power supply voltage;
a boosting circuit configured to boost said external power supply voltage to generate a boosted supply voltage; and
a write driving unit configured
to apply said external power supply voltage as said write voltage to said memory cell so that a first charge is stored in said memory cell during a first part of a write period for writing data, and
to apply said boosted supply voltage as said write voltage to said memory cell so that a second charge is stored in said memory cell during a latter part of said write period,

the stored first charge being greater in amount than the stored second charge.

5. The memory apparatus according to claim 4 , wherein:
said write driving unit includes
a decoder configured to apply said write voltage to said memory cell according to a write signal including a pulse series indicating timing to apply said write voltage to said memory cell in said write period, and
a write voltage generation circuit configured to generate said write voltage; and

said write voltage generation circuit includes
a counter configured to count the number of pulses in said write signal in said write period to obtain a count value, and
a selective relay circuit configured
to selectively relay said external power supply voltage as said write voltage to said memory cell between a start of said write period and when the count value reaches a predetermined number, and
to selectively relay said boosted supply voltage as said write voltage to said memory cell after the count value reaches the predetermined number.

6. The memory apparatus according to claim 5 , comprising a voltage controlled oscillator configured to generate an oscillation signal including a pulse series having a frequency corresponding to a voltage value of said external power supply voltage, the oscillation signal being generated as said write signal.

Assignees

• Lapis Semiconductor Co Ltd

Inventors

• Akahori Akira
• Matsui Katsuaki

Classifications

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C5/145

  Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence) · CPC title

• G11C17/123 Primary

  comprising cells having several storage transistors connected in series · CPC title

• H03H9/00

  Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators (electro-acoustic transducers such as loudspeakers, microphones or gramophone pick-ups H04R; piezoelectric, electrostrictive or magnetostrictive devices with mechanical input or output, e.g. actuators or sensors, H10N30/00, H10N35/00) · CPC title

• G11C16/30 Primary

  Power supply circuits · CPC title