Low latency write requests over a network using a pipelined I/O adapter device

Patent metadata

Field	Value
Publication number	US-9886405-B1
Application number	US-201514672658-A
Country	US
Kind code	B1
Filing date	Mar 30, 2015
Priority date	Mar 30, 2015
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

Server computers may include one or more input/output (I/O) adapter devices for communicating with a network and/or direct-attached device. The I/O adapter device may implement processes to manage write requests in a general and flexible manner. The I/O adapter device may also implement processes to manage write requests in a fast an efficient—that is, low latency—manner. Low latency write requests processes may include determining that a write packet for a write request can be processed without additional assistance from a processor, once a processor has initiated a memory access request to fetch write data and also generated protocol information for transmitting the write packet. The I/O adapter device may then process and transmit the write packet through an offload pipeline, without interrupting a processor.

First claim

What is claimed is:

1. An Input/Output (I/O) adapter device, comprising:
a first integrated circuit device including a pipeline; and
a second integrated circuit device including one or more processing cores, wherein each processing core is configured to execute a respective plurality of computer-executable instructions, wherein the plurality of computer-executable instructions, when executed by the one or more processing cores, cause the one or more processing cores to execute operations including:
receiving a request to write data over a network, wherein the request is received from a host device coupled to the I/O adapter device;
determining whether to process the request in a first mode;
upon determining to process the request in the first mode, generating protocol information for the request, wherein the protocol information includes information for transmitting a packet over the network;
initiating a request to fetch data associated with the request from the host device, wherein the request to fetch the data includes a memory access request; and
placing a packet associated with the request in the pipeline, wherein the packet includes the protocol information;

and wherein the pipeline is configured to:
execute the memory access request to fetch the data;
generate a header for the packet using the protocol information, wherein, in accordance with the first mode, the header is generated without using the one or more processing cores;
generate a payload for the packet, wherein the payload includes the data, and wherein, in accordance with the first mode, the payload is generated without using the one or more processing cores; and

transmit the packet according to the protocol information.

2. The I/O adapter device of claim 1 , wherein the pipeline is further configured to:
generate additional protocol information; and
include the additional protocol information in the header.

3. The I/O adapter device of claim 1 , wherein the plurality of computer-executable instructions, when executed by the one or more processing cores, further cause the one or more processing cores to:
receive a retransmission request for the data;
initiate an additional request to fetch the data, wherein the additional request includes an additional memory access request and additional protocol information;
and wherein the pipeline is further configured to:
execute the additional memory access request to fetch the data; and
process a retransmit packet for the retransmission request, wherein the retransmit packet includes the data and the additional protocol information, and wherein processing the retransmit packet includes preparing the retransmit packet for transmission and transmitting the retransmit packet according to the additional protocol information.

4. The I/O adapter device of claim 1 , wherein the pipeline is further configured to:
receive a retransmission request for the data;
initiate an additional request to fetch the data, wherein the additional request includes an additional memory access request;
execute the additional memory access request to fetch the data; and
process a retransmit packet for the retransmission request, wherein the retransmit packet includes the data and the protocol information, and wherein processing the retransmit packet includes preparing the retransmit packet for transmission and transmitting the retransmit write packet according to the protocol information.

5. An Input/Output (I/O) adapter device, comprising:
a pipeline circuit; and
a processor circuit comprising one or more processing cores, wherein each processing core is configured to execute a respective plurality of computer-executable instructions, wherein the plurality of computer-executable instructions, when executed by the processor circuit, causes the processor circuit to execute operations including:
receiving a write request from a host device coupled to the I/O adapter device;
determining whether to process the write request in a first mode;
upon determining to process the write request in the first mode, generating protocol information for the write request, wherein the protocol information includes information for transmitting a packet over a network;
initiating a request to fetch data associated with the write request, wherein the request to fetch the data includes a memory access request and the protocol information;

and wherein the pipeline circuit is configured to:
execute the memory access request to fetch the data;
generate a packet for the write request, wherein the packet includes the protocol information and the data, and wherein, in accordance with the first mode, the pipeline circuit generates the packet without using the processor circuit; and
transmit the packet according to the protocol information.

6. The I/O adapter device of claim 5 , wherein the processor circuit is further configured to:
generate control information for the pipeline circuit wherein the pipeline circuit uses the control information to generate the packet.

7. The I/O adapter device of claim 5 , wherein the pipeline is configured to:
generate at least a portion of the protocol information; and
use the portion of the protocol to generate the packet.

8. The I/O adapter device of claim 5 , wherein the pipeline circuit further configured to:
identify a condition requiring assistance from the processor circuit.

9. The I/O adapter device of claim 8 , wherein the condition comprises an error condition, and wherein the plurality of computer-executable instructions, when executed by the one or more processing cores, cause the one or more processing cores to:
determine a type of the error condition; and
act to resolve the error condition.

10. The I/O adapter device of claim 8 , wherein the condition comprises data compression by the processor circuit, and wherein the plurality of computer-executable instructions, when executed by the one or more processing cores, further cause the one or more processing cores to:
compress the data.

11. The I/O adapter device of claim 5 , wherein the I/O adapter device is further configured to:
receive a retransmission request for the data;
initiate an additional request to fetch the data, wherein the additional request includes an additional memory access request and additional protocol information;
execute the additional memory access request to fetch the data; and
process a retransmit packet for the retransmission request, wherein the retransmit packet includes the data and the additional protocol information, and wherein processing includes preparing the retransmit packet for transmission and transmitting the retransmit packet according to the additional protocol information.

12. The I/O adapter device of claim 5 , wherein the pipeline comprises:
a plurality of streaming components, wherein each streaming component is configured to perform one or more packet processing operations for the I/O adapter device; and
a streaming interconnect coupled to the plurality of streaming components, wherein the streaming interconnect is configured to route the write packet.

13. The I/O adapter device of claim 5 , wherein the pipeline comprises one or more of a host interface unit, a parsing and steering unit, a compression/decompression unit, an encryption/decryption unit, a splitter unit, an assembler unit, a network offload unit, a media access control unit, a payload manager, or a payload buffer.

14. A computer-implemented method, comprising:
receiving, by an Input/Output (I/O) adapter device coupled to a host device, a write request from the host device, wherein the write request is re

Assignees

• Amazon Tech Inc

Inventors

• Johnson Robert Michael
• Brooker Marc John
• Olson Marc Stephen
• Davis Mark Bradley
• Kusters Nobert Paul

Classifications

• G06F13/387 Primary

  for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system · CPC title

• G06F11/1443

  Transmit or communication errors · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F13/423

  with synchronous protocol · CPC title

• G06F2201/815

  Virtual · CPC title