Receiver, sender, method for retrieving an additional datum from a signal and method for transmitting a datum and an additional datum in a signal

Patent metadata

Field	Value
Publication number	US-9882579-B2
Application number	US-201514933349-A
Country	US
Kind code	B2
Filing date	Nov 5, 2015
Priority date	Nov 19, 2014
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A receiver includes a receiver circuit to receive a first transition in a first direction, a second transition in a second, different direction after the first transition and a third transition in the first transition after the second transition of a signal. A first time period between the first and third transitions is indicative of a datum to be received. The receiver circuit is also configured to determine a second time period between the first transition and a second transition and to determine an additional datum to be received based at least on the determined second time period between the first and second transitions. Using the determined second time period allows for more information to be received in a reliable manner.

First claim

What is claimed is:

1. A receiver comprising:
a receiver circuit configured to receive a first transition in a first direction, a second transition after the first transition in a second, different direction and a third transition after the second transition in the first direction of a signal, in which a first time period between the first and third transitions is at least partially indicating a datum to be received,
wherein the receiver circuit is further configured to determine a second time period between the first transition and the second transition and to determine an additional datum to be received based at least on the determined second time period between the first and second transitions,
wherein the receiver circuit is further configured to determine the first time period between the first transition and the third transition and to determine the datum based at least on the determined first time period,
wherein the receiver circuit is configured to determine the first transition and the third transition as transitions from a common predefined first signal level to a common predefined second signal level, wherein the common predefined first signal level is greater than the common predefined second signal level, and
wherein the receiver circuit is configured to determine the second time period based on the second transition to an intermediate signal level different from the first signal level and the second signal level.

2. The receiver according to claim 1 , wherein the receiver circuit is configured to determine the second time period being shorter than a minimum period of time after the first transition for a transition to the first level according to a single-edge nibble transmission (SENT) specification or a short PWM codes (SPC) specification for transmitting the datum.

3. The receiver according to claim 1 , wherein the receiver circuit is configured to determine the datum based on the first time period between the first and third transitions, which is variable and depending on the datum.

4. A receiver comprising:
a receiver circuit configured to receive a first transition in a first direction, a second transition after the first transition in a second, different direction and a third transition after the second transition in the first direction of a signal, in which a first time period between the first and third transitions is at least partially indicating a datum to be received,
wherein the receiver circuit is further configured to determine a second time period between the first transition and the second transition and to determine an additional datum to received based at least on the determined second time period between the first and second transitions,
wherein the receiver circuit is configured to determine the second time period between the first and second transitions based on an amplitude of the second transition, and
wherein the receiver circuit is configured to determine the additional datum based on at least two different amplitudes of the second transition.

5. A receiver comprising:
a receiver circuit configured to receive a first transition in a first direction, a second transition after the first transition in a second, different direction and a third transition after the second transition in the first direction of a signal, in which a first time period between the first and third transitions is at least partially indicating a datum to be received,
wherein the receiver circuit is further configured to determine a second time period between the first transition and the second transition and to determine an additional datum to be received based at least on the determined second time period between the first and second transitions, and
wherein the receiver circuit is configured to determine the datum based on a size of a quantization step of the first time period between the first and third transitions being smaller than or equal to a size of a quantization step of the second time period between the first and second transitions concerning the additional datum.

6. A sender comprising:
a sender circuit to determine, based on a datum to be transmitted, a first time period between a first transition in a first direction and a third transition in the first direction of a signal to be generated;
wherein the sender circuit is configured to modify, based on an additional datum to be transmitted, a predetermined second time period between the first transition and a second transition in a second, different direction of the signal, when the additional datum is different from a default value,
wherein the sender circuit is further configured to generate the signal comprising the first transition in the first direction, the second transition after the first transition in the second direction and the third transition after the second transition in the first direction based on the first and second time periods,
wherein the sender circuit is configured to generate the signal comprising the first and third transitions as transitions from a common predefined first signal level to a common predefined second level, wherein the common predefined first signal level is greater than the common predefined second signal level, and
wherein the sender circuit is configured to generate the signal comprising the second transition to an intermediate signal level different from the first signal level and the second signal level.

7. The sender according to claim 6 , wherein the sender circuit is configured to determine the first time period based on the datum as a variable time period depending on the datum.

8. A sender comprising:
a sender circuit to determine, based on a datum to be transmitted, a first time period between a first transition in a first direction and a third transition in the first direction of a signal to be generated;
wherein the sender circuit is configured to modify, based on an additional datum to be transmitted, a predetermined second time period between the first transition and a second transition in a second, different direction of the signal, when the additional datum is different from a default value,
wherein the sender circuit is further configured to generate the signal comprising the first transition in the first direction, the second transition after the first transition in the second direction and the third transition after the second transition in the first direction based on the first and second time periods,
wherein the sender circuit is configured to further determine an amplitude for the second transition based on the additional datum from at least two different amplitudes for the second transition, and
wherein the sender circuit is configured to generate the second transition of the signal with the determined amplitude for the second transition.

9. The sender according to claim 8 , wherein the sender circuit is configured to generate the signal comprising the first and third transitions as transitions from a common predefined first signal level to a common predefined second level, wherein the common predefined first signal level is greater than the common predefined second signal level.

10. The sender according to claim 9 , wherein the sender circuit is configured to modify the second time period being shorter than a minimum period of time after the first transition for a transition to the first level according to a single-edge nibble transmission (SENT) specification or a short PWM codes (SPC) specification for transmitting the datum, when the additional datum indicates the second time period being shorter than the minimum time.

11. A sender comprising:
a sender circuit to determine, based on a datum to be transmitted, a first time period between a firs

Assignees

• Infineon Technologies Ag

Inventors

• Hammerschmidt Dirk

Classifications

• H04B1/16

  Circuits · CPC title

• H04B1/04 Primary

  Circuits · CPC title

• H03M5/02 Primary

  Conversion to or from representation by pulses · CPC title

• H03M5/22

  Conversion to or from representation by sinusoidal signals · CPC title

• H04B14/026

  using pulse time characteristics modulation, e.g. width, position, interval · CPC title