Selector device for a non-volatile memory cell

Patent metadata

Field	Value
Publication number	US-9882125-B2
Application number	US-201615040981-A
Country	US
Kind code	B2
Filing date	Feb 10, 2016
Priority date	Feb 11, 2015
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

Memory cells and methods of forming memory cells are disclosed. The memory cell includes a substrate and a select transistor. The select transistor includes a gate disposed over the substrate between first and second source/drain (S/D) terminals. The first and second S/D terminals are configured such that a resistance at the second S/D terminal is higher than a resistance at the first S/D terminal. A dielectric layer disposed over the substrate includes a plurality of inter level dielectric (ILD) layers. A lower portion of the dielectric layer includes a first contact level and a first metal level. A first contact plug disposed within the first contact level connects the first S/D terminal to a first metal line in the first metal level. A magnetic tunnel junction (MTJ) element is disposed directly on and in contact with a top of the first metal line.

First claim

What is claimed is:

1. A memory cell comprising:
a crystalline-on-insulator (COI) substrate, wherein the COI substrate includes a surface crystalline layer which is separated from a bulk crystalline by a buried insulator layer;
a select transistor on the COI substrate, wherein the select transistor includes a gate disposed over the substrate and between first and second source/drain (S/D) terminals, wherein
a first and second sidewall of the gate is completely covered by dielectric liners,
dielectric spacers are disposed adjacent to the first and second sidewalls of the gate, wherein each dielectric spacer covers a side of the dielectric liners, and
the first and second S/D terminals are asymmetric S/D terminals and are configured such that a resistance at the second S/D terminal is higher than a resistance at the first S/D terminal;

a ground plane structure disposed below the buried insulator layer and within the bulk crystalline layer of the COI substrate;
a dielectric layer disposed over the COI substrate, wherein the dielectric layer comprises a plurality of inter level dielectric (ILD) layers, a lower portion of the dielectric layer includes a first contact level and a first metal level, wherein a first contact plug disposed within the first contact level connects the first S/D terminal to a first metal line in the first metal level; and
a magnetic tunnel junction (MTJ) element disposed directly on and in contact with a top of the first metal line.

2. The memory cell of claim 1 wherein the first contact level comprises a second contact plug connecting the second S/D terminal to a second metal line disposed in the first metal level, wherein the second metal line is a source line (SL).

3. The memory cell of claim 1 wherein the first and second S/D terminals include first and second lightly doped diffusion (LDD) regions underlapping a portion of first and second sides of the gate.

4. The memory cell of claim 3 wherein the first S/D terminal includes a heavily doped raised S/D portion disposed over the LDD region and the second S/D terminal is devoid of a heavily doped raised S/D portion.

5. The memory cell of claim 3 wherein each of the first and second S/D terminals includes a heavily doped raised S/D portion over a heavily doped base S/D portion.

6. The memory cell of claim 5 wherein each of the raised S/D portions of the first and second S/D terminals comprises a heavily doped epitaxial layer disposed on the COI substrate and over the base S/D portion.

7. The memory cell of claim 5 wherein the ground plane structure comprises a local ground plane (LGP) underlapping the first or second S/D terminal.

8. The memory cell of claim 7 wherein the LGP underlaps the first S/D terminal without underlapping the second S/D terminal, wherein the LGP comprises same polarity type dopants as the heavily doped base S/D portion of the first.

9. The memory cell of claim 7 wherein the LGP underlaps the second S/D terminal without underlapping the first S/D terminal, wherein the LGP comprises different polarity type dopants from the heavily doped base S/D portion of the second S/D terminal.

10. The memory cell of claim 3 wherein each of the first and second S/D terminals comprises a heavily doped epitaxial layer disposed on the COI substrate, wherein the heavily doped epitaxial layer defines a raised S/D portion of each of the first and second S/D terminals.

11. The memory cell of claim 10 comprising a metal silicide disposed on each raised S/D portion of the first and second S/D terminals, wherein an interface of each metal silicide and S/D portion includes a Schottky Barrier Height (SBH), wherein the SBH of the first S/D terminal is lower than the SBH of the second S/D terminal.

12. The memory cell of claim 10 wherein each of the first and second S/D terminals is devoid of a heavily doped base S/D portion disposed in the COI substrate.

13. The memory cell of claim 1 wherein the second S/D terminal is a source terminal and the first S/D terminal is a drain terminal, wherein the higher resistance at the source terminal relative to the resistance at the drain terminal leads to unequal bidirectional write currents flowing through the memory cell during write operations.

14. The memory cell of claim 3 wherein the first and second S/D terminals are devoid of a heavily doped diffusion region disposed within the surface crystalline layer of the COI substrate.

15. The memory cell of claim 4 comprising:
a first metal silicide contact disposed on the raised S/D portion of the first S/D terminal; and
a second metal silicide contact disposed directly on the LDD region of the second S/D terminal, wherein the second metal silicide contact is in contact with the surface crystalline layer of the COI substrate.

16. The memory cell of claim 1 wherein the ground plane structure extends to underlap the gate and the first and second S/D terminals of the select transistor.

17. A memory cell comprising:
a crystalline-on-insulator (COI) substrate, wherein the COI substrate includes a surface crystalline layer which is separated from a bulk crystalline layer by a buried insulator layer;
a select transistor on the substrate, the select transistor includes a gate disposed over the substrate between first and second source/drain (S/D) terminals, wherein the first and second S/D terminals are asymmetric S/D terminals and are configured such that a resistance at the second S/D terminal is higher than a resistance at the first S/D terminal;
a dielectric layer disposed over the substrate, wherein the dielectric layer comprises a plurality of inter level dielectric (ILD) layers, a lower portion of the dielectric layer includes a first contact level and a first metal level, a first contact plug disposed within the first contact level connects the first S/D terminal to a first metal line in the first metal level;
a magnetic tunnel junction (MTJ) element disposed directly on and in contact with a top of the first metal line; and
wherein a ground plane structure is disposed below the buried insulator layer, wherein a top of the ground plane structure is contiguous with a bottom of the insulator layer and the ground plane structure extends across cell regions to underlap the entire buried insulator layer.

18. A memory cell comprising:
a substrate;
a select transistor on the substrate, wherein the select transistor comprises a gate disposed over the substrate, wherein a source terminal and a drain terminal of the select transistor are disposed adjacent to first and second sides of the gate, wherein the source and drain terminals comprise an asymmetrical configuration, wherein the source terminal is configured with a higher resistance relative to a resistance at the drain terminal, wherein the drain terminal is defined by a lightly doped drain portion and a heavily doped drain portion, wherein
the lightly doped drain portion is disposed within the substrate and adjacent to the first side of the gate, and
the heavily doped drain portion is disposed on the substrate, wherein the heavily doped drain portion is positioned completely over the lightly doped drain portion;

a dielectric layer disposed over the substrate, wherein the dielectric layer comprises a plurality of inter level dielectric (ILD) layers, wherein a lower portion of the dielectric layer comprises a first contact level and a first metal level over the first contact level, wherein a first contact plug is disposed in the first contact level and a first metal pad is disposed in the first metal level; and
a magnetic tunne

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Toh Eng Huat
• Quek Kiok Boone Elgin

Classifications

• H10D30/608 Primary

  having non-planar bodies, e.g. having recessed gate electrodes · CPC title

• H01L43/12 Primary

  Electricity · mapped topic

• H01L29/7848

  Electricity · mapped topic

• H01L29/7834

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic