Semiconductor device including Fin-FET and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9882029-B2
Application number	US-201615208393-A
Country	US
Kind code	B2
Filing date	Jul 12, 2016
Priority date	Dec 22, 2014
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A semiconductor device includes a first fin structure for a first fin field effect transistor (FET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
forming a fin structure including a lower layer, an intermediate layer disposed over the lower layer and an upper layer disposed over the intermediate layer;
forming a protective layer on at least sidewalls of the fin structure to sidewalls of the intermediate layer, the protective layer being made of a material that prevents an underlying layer from oxidation;
forming an isolation insulating layer so that the fin structure with the protective layer is embedded in the isolation insulating layer;
removing a part of the upper layer, a part of the protective layer covering the upper layer and the isolation insulating layer so that an opening is formed in the isolation insulating layer and the protective layer remains on sidewalls of the lower layer and the sidewalls of the intermediate layer; and
forming a channel layer in the opening,
wherein after the channel layer is formed, the lower layer and the protective layer are embedded in the isolation insulating layer.

2. The method of claim 1 , wherein:
the protective layer remains on a sidewall of a bottom part of the upper layer, and
a bottom of the opening is spaced apart from the protective layer.

3. The method of claim 2 , wherein the removing a part of the protective layer includes:
forming a sacrificial layer so that the fin structure with the protective layer is embedded in the sacrificial layer;
reducing a thickness of the sacrificial layer;
removing the part of the protective layer covering the upper layer so that the protective layer remains on the sidewalls of the lower layer, the sidewalls of the intermediate layer and the sidewalls of the bottom part of the upper layer; and
removing the sacrificial layer of which thickness has been reduced.

4. The method of claim 3 , wherein the sacrificial layer is a resin layer.

5. The method of claim 2 , wherein:
the removing a part of the protective layer includes:
forming a first insulating layer;
reducing a thickness of the first insulating layer; and
removing the part of the protective layer covering the upper layer so that the protective layer remains on the sidewalls of the lower layer, the sidewalls of the intermediate layer and the sidewalls of the bottom part of the upper layer, and

the forming an isolation insulating layer includes:
forming a second insulating layer on the first insulating layer of which thickness has been reduced.

6. The method of claim 2 , wherein the protective layer does not cover a sidewall of the channel layer and is spaced apart from the channel layer.

7. The method of claim 2 , wherein the protective layer is spaced apart from the bottom of the opening by a distance of 2 nm to 20 nm.

8. The method of claim 1 , wherein the channel layer includes SiGe.

9. The method of claim 1 , wherein the intermediate layer includes SiGe.

10. The method of claim 1 , wherein a thickness of the protective layer is 1 nm to 10 nm.

11. The method of claim 1 , wherein the protective layer is made of silicon nitride.

12. The method of claim 1 , wherein the forming the fin structure comprises:
forming a first semiconductor layer over a substrate, and forming a second semiconductor layer over the first semiconductor layer, thereby forming a stacked structure of the second semiconductor layer, the first semiconductor layer and the substrate; and
forming the fin structure by patterning the stacked structure such that the patterned substrate becomes the lower layer, the patterned first semiconductor layer becomes the intermediate layer and the patterned second semiconductor layer becomes the upper layer.

13. A method for manufacturing a semiconductor device, comprising:
forming a first fin structure and a second fin structure, each of the first and second fin structures including a lower layer, an intermediate layer disposed over the lower layer and an upper layer disposed over the intermediate layer;
forming an oxide layer on the intermediate layer of the second fin structure, while protecting the intermediate layer of the first fin structure from oxidization;
forming a protective layer over the second fin structure having the oxide layer on the intermediate layer and over the first fin structure;
removing an upper part of the protective layer covering the upper layer of the first fin structure and an upper part of the protective layer covering the upper layer of the second fin structure, so that the protective layer remains on a sidewall of the lower layer, a sidewall of the oxide layer on the intermediate layer and a sidewall of a bottom part of the upper layer of the second fin structure and the protective layer remains on a sidewall of the lower layer, a sidewall of the intermediate layer and a sidewall of a bottom part of the upper layer of the first fin structure;
forming an isolation insulating layer so that the first and second fin structures with the protective layer of which upper parts are removed are embedded in the isolation insulating layer;
removing a part of the upper layer of the first fin structure and the isolation insulating layer so that an opening is formed in the isolation insulating layer; and
forming a channel layer in the opening.

14. The method of claim 13 , wherein the intermediate layer includes SiGe.

15. The method of claim 13 , wherein the channel layer includes SiGe.

16. The method of claim 13 , wherein the removing the upper parts of the protective layer includes:
forming a sacrificial layer so that the first and second fin structures with the protective layer are embedded in the sacrificial layer;
reducing a thickness of the sacrificial layer;
removing the upper parts of the protective layer; and
removing the sacrificial layer of which thickness has been reduced.

17. The method of claim 16 , wherein the sacrificial layer is a resin layer.

18. The method of claim 13 , wherein:
the removing the upper parts of the protective layer includes:
forming a first insulating layer;
reducing a thickness of the first insulating layer; and
removing the upper part of the protective layer, and

the forming the isolation insulating layer includes:
forming a second insulating layer on the first insulating layer of which thickness has been reduced.

19. The method of claim 13 , wherein the protective layer does not cover a sidewall of the channel layer and is spaced apart from the channel layer.

20. A method for manufacturing a semiconductor device, comprising:
forming a fin structure including a lower layer, an intermediate layer disposed over the lower layer and an upper layer disposed over the intermediate layer;
forming a protective layer over the fin structure;
removing an upper part of the protective layer covering the upper layer of the fin structure, so that the protective layer remains on a sidewall of the lower layer, a sidewall of the intermediate layer and a sidewall of a bottom part of the upper layer of the fin structure;
forming an isolation insulating layer so that the fin structure with the protective layer of which upper part is removed is embedded in the isolation insulating layer;
removing a part of the upper layer of the fin structure and the isolation insulating layer so that an opening is formed in the isolation insulating layer;
forming a channel layer in the opening; and
forming a gate structure over the channel layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Gin-Chen
• Hsu Tzu-Hsiang
• Hsu Chia-Jung
• Yang Feng-Cheng
• Tsai Teng-Chun

Classifications

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H01L29/165

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L29/6681

  Electricity · mapped topic