Method of fabricating gate electrode using a treated hard mask

Patent metadata

Field	Value
Publication number	US-9881840-B2
Application number	US-201113157179-A
Country	US
Kind code	B2
Filing date	Jun 9, 2011
Priority date	Jun 9, 2011
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided on the hard mask layer to transform the hard mask layer to be more resistant to wet etching solution. A patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.

First claim

What is claimed is:

1. A method of fabricating an integrated circuit device, the method comprising:
providing a substrate;
forming a material layer over the substrate;
forming a hard mask layer over the material layer;
providing a treatment to the hard mask layer to introduce dopants therein, wherein a dose of the treatment is not less than about 1E16 ions/cm 2 ;
annealing the treated hard mask layer; and
patterning the treated hard mask layer and the material layer.

2. The method of claim 1 , wherein the hard mask layer is silicon oxide.

3. The method of claim 1 , wherein the hard mask layer has a thickness less than or equal to approximately 500 Angstroms.

4. The method of claim 1 , wherein the dopants comprise silicon (Si).

5. The method of claim 1 , wherein the dopants comprise carbon (C) and boron (B).

6. The method of claim 1 , wherein the treatment is performed by at least one of ion beams or plasma doping (PLAD).

7. The method of claim 6 , wherein a process flow of the plasma doping is in a range from about 50 sccm to about 500 sccm and a process pressure of the plasma doping is in a range from about 5 mTorr to about 50 mTorr.

8. The method of claim 6 , wherein the plasma doping is performed using a radio frequency power in a range from about 100 watts (W) to about 1000 W.

9. The method of claim 6 , wherein the plasma doping is performed using a pulsed plasma with a duty ratio (power-on-time/total-time) in a range from about 5% to about 95% and for a duration in a range from about 10 seconds to about 5 minutes.

10. The method of claim 1 , wherein the treated hard mask layer has a dopant concentration equal to or greater than about 5E21 atoms/cm 3 .

11. The method of claim 1 , further comprising a step of performing LDD regions in the substrate by an implantation process utilizing a tilt-angle of approximately 25° to about 30°.

12. The method of claim 1 , wherein annealing the treated hard mask layer comprises annealing the treated hard mask layer at an annealing temperature ranging from about 600° C. to about 1350° C.

13. A method for manufacturing a gate structure, the method comprising:
forming a gate electrode layer over a substrate;
forming a hard mask layer over the gate electrode layer;
providing a treatment on the hard mask layer to form a treated hard mask layer, the treatment comprising
introducing dopants into the hard mask layer with a dose not less than about 1E16 ions/cm 2 ; and
annealing the hard mask layer; and

patterning the treated hard mask layer and the gate electrode layer.

14. The method of claim 13 , wherein a temperature of the step of annealing ranges from about 900° C. to about 1350° C.

15. The method of claim 13 , wherein the dopants comprise boron and carbon.

16. The method of claim 13 , wherein the dopants comprise silicon.

17. The method of claim 13 , wherein the treatment is performed by ion beams or plasma doping (PLAD).

18. The method of claim 13 , wherein the treated hard mask layer has a dopant concentration equal to or greater than about 5E21 atoms/cm 3 .

19. A method for manufacturing a gate electrode, the method comprising:
providing a substrate;
forming a gate electrode layer over the substrate;
forming a first hard mask layer over the gate electrode layer;
treating the first hard mask layer to form a first treated hard mask layer;
forming a second hard mask layer over the first treated hard mask layer;
treating the second hard mask layer to form a second treated hard mask layer;
patterning the first treated hard mask layer, the second treated hard mask layer, and the gate electrode layer to form a gate structure of PMOS device and a gate structure of NMOS device;
forming n-type strained source/drain (NSSD) regions in the substrate, wherein the NSSD regions are adjacent to edges of the gate structure of NMOS device;
forming p-type strained source/drain (PSSD) regions in the substrate, wherein the PSSD regions are adjacent to edges of the gate structure of PMOS device;
forming n-type lightly-doped source/drain (NLDD) regions in or under the NSSD regions by a first tilt-angle ion implantation; and
forming p-type lightly-doped source/drain (PLDD) regions in the PSSD regions by a second tilt-angle ion implantation.

20. The method of claim 19 , wherein an etching rate of the first or the second treated hard mask layer in a 1/100 diluted hydrofluoric (DHF) solution at room temperature is less than about 20 Å/min.

Assignees

• Huang Yu-Lien
• Fang Ziwei
• Wang Tsan-Chun
• Wu Chii-Ming
• Tsai Chun Hsiung
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Yu-Lien
• Fang Ziwei
• Wang Tsan-Chun
• Wu Chii-Ming
• Tsai Chun Hsiung

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P30/40

  into insulating materials · CPC title

• H01L21/823807

  Electricity · mapped topic

• H01L21/0337

  Electricity · mapped topic