Semiconductor devices having multiple gate structures and methods of manufacturing such devices

Patent metadata

Field	Value
Publication number	US-9881838-B2
Application number	US-201715413472-A
Country	US
Kind code	B2
Filing date	Jan 24, 2017
Priority date	May 21, 2015
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of first active fins and a plurality of first sacrificial gate structures in a first region of a substrate;
forming a plurality of second active fins and a plurality of second sacrificial gate structures in a second region of the substrate;
forming first preliminary spacers on sidewalls of the respective first sacrificial gate structures, the first preliminary spacers including a first spacer and a first sacrificial spacer;
etching upper portions of the first active fins using the first preliminary spacers as an etch mask to form first recess regions at opposed sides of the first sacrificial gate structures;
removing the first sacrificial spacers;
epitaxially growing first embedded source/drain regions in the first recess regions;
forming second preliminary spacers on sidewalls of the respective second sacrificial gate structures, the second preliminary spacers including a second spacer, a third spacer, and a second sacrificial spacer;
etching upper portions of the second active fins using the second preliminary spacers as an etch mask to form second recess regions at opposed sides of the second sacrificial gate structures;
removing the second sacrificial spacers; and
epitaxially growing second embedded source/drain regions in the second recess regions.

2. The method of claim 1 , wherein forming the first preliminary spacers comprises:
forming a first insulating layer on the first sacrificial gate structures and on the second sacrificial gate structures;
forming a second insulating layer on the first insulating layer, the second insulating layer having an etch selectivity with respect to the first insulating layer;
performing an etch-back process on the second insulating layer to form the first sacrificial spacers; and
performing an etch-back process on the first insulating layer to form the first spacers.

3. The method of claim 1 , wherein the first spacers have L-shaped cross-sections.

4. The method of claim 1 , wherein the first sacrificial spacers are removed via a wet etch process using at least one solution selected from a diluted HF solution and a buffered oxide etchant (BOE) solution.

5. The method of claim 1 , wherein the first sacrificial spacers are removed via a dry etch process using at least one gas selected from NH 3 and NF 3 .

6. The method of claim 2 , wherein the second insulating layer is removed in the second region during the removal of the first sacrificial spacers, and
wherein the first insulating layer in the second region is not removed during the removal of the first sacrificial spacers.

7. The method of claim 1 , wherein forming the second preliminary spacers comprises:
forming a third insulating layer on the substrate;
forming a fourth insulating layer on the third insulating layer, the fourth insulating layer having an etch selectivity with respect to the third insulating layer;
performing an etch-back process on the fourth insulating layer in the second region to form the second sacrificial spacers; and
performing an etch-back process on the third and first insulating layers in the second region to form the third and second spacers, respectively.

8. The method of claim 1 , wherein each of the second and third spacers have L-shaped cross-sections.

9. The method of claim 1 , wherein the second sacrificial spacers are removed via a wet etch process using at least one solution selected from a diluted HF solution and a buffered oxide etchant (BOE) solution.

10. The method of claim 1 , wherein the second sacrificial spacers are removed via a dry etch process using at least one gas selected from NH 3 and NF 3 .

11. The method of claim 7 , wherein the fourth insulating layer in the first region is removed during the removal of the second sacrificial spacers, and
wherein the third insulating layer in the first region is not removed during the removal of the second sacrificial spacers.

12. The method of claim 1 , further comprising:
forming an etch stop layer on the substrate after forming the second embedded source/drain regions;
forming an interlayer dielectric layer on the etch stop layer;
planarizing the interlayer dielectric layer to expose upper surfaces of the first and second sacrificial gate structures;
removing the first sacrificial gate structures and the second sacrificial gate structures to form a third recess regions and a fourth recess regions, respectively; and
forming first gate structures and second gate structures in the third recess regions and the fourth recess regions, respectively.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Yoon Hae
• Lee Jin Wook
• Jung Jong Ki
• Kang Myung Il
• Yang Kwang Yong
• Lee Kwan Heum
• Lee Byeong Chan

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H01L21/823828

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic