IR-aware sneak routing

Patent metadata

Field	Value
Publication number	US-9881118-B2
Application number	US-201414576108-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Dec 20, 2013
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A method for routing a circuit device having an array of bump pads includes identifying a routing direction associated with a bump, generating a power strap and a ground strap based on the routing direction, forming a routing channel in accordance with the routing direction, setting a start point and an endpoint in the routing channel, and connecting the start point and the endpoint using a wire within the routing channel. The method further includes placing the start point to a power or ground strap in response to a target power/ground ratio.

First claim

What is claimed is:

1. A computer-implemented method for routing a flip-chip circuit device having an array of bumps, the computer-implemented method comprising:
identifying, using the computer, a routing direction associated with a bump included in the flip-chip circuit device when the computer is invoked to identify the routing direction;
forming, using the computer, a routing channel in accordance with the routing direction;
setting, using the computer, a start point and an endpoint in the routing channel; and
connecting, using the computer, the start point and the endpoint using a wire.

2. The computer-implemented method of claim 1 , wherein identifying the routing direction is based on one or more pre-routed nets associated with the bump.

3. The computer-implemented method of claim 1 , wherein forming the routing channel comprises:
setting a boundary around the center of the bump;
extending the boundary lengthwise in the routing direction;
determining whether the boundary is extendable in the routing direction;
if the boundary is extendable in the routing direction:
extending the boundary until it contacts a power/ground (P/G) bump, a P/G strap, or a barrier; and
if the boundary is not extendable in the routing direction:
terminating the boundary extension.

4. The computer-implemented method of claim 3 , further comprising:
extending the boundary widthwise in a direction orthogonal to the routing direction until the boundary reaches the center of adjacent bumps arranged lengthwise in the routing direction.

5. The computer-implemented method of claim 4 , wherein the boundary straddles two adjacent P/G straps.

6. The computer-implemented method of claim 5 , further comprising:
calculating a routing area within the boundary, the routing area having a first edge and a second edge opposite the first edge in the routing direction, the first edge associated with the start point and the second edge associated with the endpoint.

7. The computer-implemented method of claim 6 , wherein the endpoint is located at the center of the second edge, and the wire interconnecting the start point and the endpoint comprises a plurality of partially overlapped segments, each of the overlapped segments having a regularly polygonal shape.

8. The computer-implemented method of claim 7 , wherein the regularly polygonal shape is a rectangle or an octagon.

9. The computer-implemented method of claim 5 , wherein the start point is electrically connected to a power strap or a ground strap in response to a target power/ground ratio.

10. The computer-implemented method of claim 1 , further comprising:
sneaking the wire around bumps in the routing channel.

11. A non-transitory computer readable medium comprising instructions which when executed by a computer cause the computer to:
identify a routing direction associated with a bump pad included in a flip-chip design when the computer is invoked to identify the routing direction;
form a routing channel in accordance with the routing direction;
set a start point and an endpoint in the routing channel; and
connect the start point and the endpoint using a wire within the routing channel.

12. The non-transitory computer readable medium of claim 11 , wherein the routing direction is identified based on one or more pre-routed nets associated with the bump pad.

13. The non-transitory computer readable medium of claim 11 , wherein the instructions that cause the computer to form the routing channel further cause the computer to:
set a boundary around the center of the bump pad;
extend the boundary lengthwise in the routing direction;
determine whether the boundary is extendable in the routing direction;
if the boundary is extendable in the routing direction:
extend the boundary until the boundary is in contact with a power/ground (P/G) bump pad, a P/G strap, or a barrier; and
if the boundary is not extendable in the routing direction:
terminate the boundary extension.

14. The non-transitory computer readable medium of claim 13 , further comprising instructions that cause the computer to:
extend the boundary widthwise in a direction orthogonal to the routing direction until the boundary reaches the center of adjacent bump pads arranged lengthwise in the routing direction, wherein the boundary straddles two adjacent P/G straps.

15. The non-transitory computer readable medium of claim 14 , further comprising instructions that cause the computer to:
calculate a routing area within the boundary, wherein:
the routing area comprises a first edge and a second edge opposite the first edge in the routing direction, the first edge associated with the start point and the second edge associated with the endpoint;
the endpoint is located at the center of the second edge, and
the wire interconnecting the start point and the endpoint comprises a plurality of partially overlapped segments, each of the overlapped segments having a regularly polygonal shape.

16. The non-transitory computer readable medium of claim 11 , further comprising instructions that cause the computer to:
sneak the wire around bump pads in the routing channel.

17. A system for routing a flip-chip circuit having an array of bump pads, the system comprising:
at least one processing unit configured to:
identify a routing direction associated with a bump pad included in the flip-chip circuit, when the system is invoked to identify the routing direction;
form a routing channel in response to the routing direction;
set a start point and an endpoint in the routing channel; and
connect the start point and the endpoint using a wire within the routing channel.

18. The system of claim 17 , wherein the routing channel has a rectangular shape straddling a power strap and a ground strap.

19. The system of claim 18 , wherein the start point is electrically connected to the power strap or the ground strap in response to a target power/ground ratio.

20. The system of claim 19 , wherein the power trap or the ground trap is associated with a respective core power bump or a core ground bump, and the at least one processing unit is further configured to:
sneak the wire around bumps in the routing channel along the routing direction toward an I/O region.

21. The system of claim 17 , wherein the at least one processing unit is further configured to:
calculate a routing area with the routing channel.

22. The system of claim 21 , wherein the routing area comprises:
a first edge associated with the start point;
a second edge opposite the first edge in the routing direction and associated with the endpoint;
the endpoint located at the center of the second edge; and
the wire interconnecting the start point and the endpoint comprising a plurality of partially overlapped segments.

23. The system of claim 22 , wherein each of the overlapped segments comprises a regularly polygonal shape.

24. The system of claim 23 , wherein the regularly polygonal shape is a rectangle or an octagon.

Assignees

• Synopsys Taiwan Co Ltd
• Synopsys Inc

Inventors

• Chiu Hsien-Shih
• Hu Kai-Shun

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/05 Primary

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title