Configurable sponge function engine

Patent metadata

Field	Value
Publication number	US-9880960-B1
Application number	US-201514869775-A
Country	US
Kind code	B1
Filing date	Sep 29, 2015
Priority date	Jun 19, 2015
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A configurable sponge function engine. The configurable engine includes a state register having bitrate and capacity sections, each having a variable size, where a sum of the bitrate and capacity sizes is fixed. A controller generates a bitrate size indication. A configurable message processor receives an input message from an input bus, receives the size indication, fragments the input message into fragmented blocks of a size specified by the size indication, and converts the blocks to a bus width of the bitrate and capacity sizes. An iterative calculator receives the blocks, performs iterative processing operations on the blocks, and stores a result of each operation in the state register overwriting a previous register value. An output adaptor receives a value stored in the state register after the block corresponding to the end of the input message is processed and outputs the register value converted to have an output bus width.

First claim

What is claimed is:

1. A configurable sponge function engine, comprising:
a state register comprising a bitrate section having a variable bitrate size, and a capacity section having a variable capacity size, wherein a sum of the bitrate and capacity sizes is fixed;
a controller configured to generate a bitrate size indication;
a configurable message processor configured to:
receive an input message from an input bus having a width;
receive the bitrate size indication from the controller;
fragment the input message into fragmented blocks of a size specified by the bitrate size indication; and
convert the fragmented blocks to a bus width equal to the sum of the bitrate and capacity sizes;

an iterative calculator configured to:
receive the fragmented blocks from the configurable message processor;
perform iterative processing operations on the fragmented blocks; and
overwrite a previous state register value with a result of each iterative processing operation until a fragmented block corresponding to an end of the input message is processed; and

an output size adaptor configured to:
receive a value stored in the state register after the fragmented block corresponding to the end of the input message is processed;
convert the state register value to have a width of an output bus; and
output the converted state register value on the output bus.

2. The configurable sponge function engine of claim 1 wherein the configurable message processor is further configured to:
determine whether a size of the input message is evenly divisible by the bitrate size; and
apply a padding scheme to the input message to create a padded input message having a size that is evenly divisible by the bitrate size;
wherein the controller is configured to provide one or more control signals to alter the padding scheme applied to the input message.

3. The configurable sponge function engine of claim 1 wherein when the iterative calculator performs iterative processing operations, the iterative calculator is further configured to:
receive one of the fragmented blocks from the configurable message processor;
apply an XOR operation on the fragmented block and on a value stored in the state register to generate an XOR result;
replace a capacity portion of the XOR result with values from the corresponding capacity section of the state register to create a modified XOR result;
apply a number of permutation iterations of a permutation function to the modified XOR result to generate a permuted result; and
store the permuted result the state register.

4. The configurable sponge function engine of claim 3 wherein the controller is further configured to:
determine that an aggregate size of output state register values is less than a desired output size; and
as a result of the determining:
cause the iterative calculator to apply the permutation function to a current state register value to generate a permuted result and store the permuted result in the state register.

5. The configurable sponge function engine of claim 1 , wherein the configurable sponge function engine is part of a microprocessor, an application-specific integrated circuit (ASIC), a system-on-a-chip (SoC), or a field-programmable gate array (FPGA).

6. A system, comprising:
a configurable sponge function engine comprising:
a controller configured to generate a variable fragment size indication;
a configurable message processor configured to receive the fragment size indication from the controller and to fragment an input message into fragmented blocks of a size specified by the fragment size indication;
an iterative calculator configured to perform iterative processing operations on the fragmented blocks and overwrite a previous value of a state register with a result of each iterative processing operation until a fragmented block corresponding to an end of the input message is processed; and
an output size adaptor configured to receive a value stored in the state register after the fragmented block corresponding to the end of the input message is processed, and to output on an output bus the state register value, wherein the state register value is adjusted to have a width of the output bus.

7. The system of claim 6 wherein when the iterative calculator performs iterative processing operations, the iterative calculator is further configured to:
receive one of the fragmented blocks from the configurable message processor;
apply an XOR operation on the fragmented block and on a value stored in the state register to generate an XOR result;
apply a number of permutation iterations of a permutation function to the result of the XOR operation to generate a permuted result; and
update the state register to store the permuted result.

8. The system according to claim 7 wherein the controller is configured to generate a permutation control signal and the iterative calculator is configured to either apply a single permutation function per each permutation iteration or multiple permutation functions per each permutation iteration based on the permutation control signal.

9. The system of claim 7 wherein the controller is further configured to:
determine that an aggregate size of output state register values is less than a desired output size; and
as a result of the determining:
cause the iterative calculator to apply the permutation function to the current state register value to generate a permuted result and store the permuted result in the state register.

10. The system of claim 6 wherein the configurable message processor is further configured to:
determine that a size of the input message is evenly divisible by the fragment size indication; and
apply a padding scheme to the input message to create a padded input message having a size that is evenly divisible by the fragment size indication value;
wherein the controller is configured to provide one or more control signals to alter the padding scheme applied to the input message.

11. The system according to claim 10 wherein the configurable fragmentation module is configured to perform an initial padding operation on fragmented blocks and then replace at least a part of content that was initially padded by padding content supplied by the controller.

12. The system of claim 6 further comprising a server coupled to the configurable sponge function engine and configured to execute a first virtual machine and a second virtual machine, wherein the controller is configured to:
generate a first fragment size indication when accessed by the first virtual machine; and
generate a second fragment size indication when accessed by the second virtual machine,
wherein the first and second fragment size indications are not equal.

13. The system of claim 6 , wherein the configurable sponge function engine is part of a microprocessor, an application-specific integrated circuit (ASIC), a system-on-a-chip (SoC), or a field-programmable gate array (FPGA).

14. A method for calculating a sponge function, comprising:
receiving, by a configurable message processor from a controller, a fragment size indication configured to be varied;
receiving an input message from an input bus having a width;
fragmenting the input message into fragmented blocks of a size specified by the fragment size indication;
applying iterative processing operations on the fragmented blocks and on a state register value, the state register value being stored in a state register;
storing a result of each iterative processing operation in the state register as an updated value until a fragmented block corresponding to an end of the input messa

Assignees

• Amazon Tech Inc

Inventors

• Diamant Ron
• Weber Ori
• Shaked Omer

Classifications

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title