Method and apparatus for adapting the data transmission security in a serial bus system

Patent metadata

Field	Value
Publication number	US-9880956-B2
Application number	US-201214110179-A
Country	US
Kind code	B2
Filing date	Mar 29, 2012
Priority date	Apr 6, 2011
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

In a bus system that includes at least two subscribed data processing units that exchange messages via a bus in a serial data transmission, the transmitted messages are of a logical structure that includes a start-of-frame bit, an arbitration field, a control field, a data field, a CRC field, an acknowledge field and an end-of-frame sequence, the control field including a data length code, which contains information regarding the length of the data field. The CRC field of the messages can include any of two or more different numbers of bits depending on a value of an associated switchover condition (UB 3 ).

First claim

What is claimed is:

1. A method for serial data transmission processing in a bus system that includes a bus and at least two subscribed data processing units that are configured to exchange messages via the bus, the method comprising:
obtaining a message transmitted by one of the at least two subscribed data processing units and on the bus, wherein the message is structured according to a predefined logical structure that includes a start-of-frame bit, an arbitration field, a control field including a data length code, a data field, a CRC field, an acknowledge field, and an end-of-frame sequence;
determining, by a computer processor, a value of a first switchover condition, the value of the switchover condition being based on one of a bit and a bit combination in the message; and
based on the determined value of the switchover condition, determining a number of bits included in the CRC field.

2. The method of claim 1 , wherein the processor is configured for processing CRC fields of a plurality of messages, which CRC fields differ with respect to a respective number of bits included in the respective CRC fields.

3. The method of claim 1 , wherein the logical structure is according to the CAN standard ISO 11898-1.

4. The method of claim 1 , further comprising:
determining, based on an identification in at least one of the arbitration field and the control field, whether the message is of a type that the number of bits of the CRC field of which is dependent on the value of the switchover condition.

5. The method of claim 4 , wherein the value of the switchover condition is ascertained based on the identification, the message being differently processed depending on the determined number of bits included in the CRC field.

6. The method of claim 5 , wherein content of the data length code is also determined based on the identification.

7. The method of claim 1 , wherein the value of the switchover condition is ascertained based on content of the data length code, the message being differently processed depending on the determined number of bits included in the CRC field.

8. The method of claim 1 , further comprising:
responsive to obtaining a beginning of the obtained message, initiating calculation of at least two CRC checksums in parallel using different generator polynomials; and
selecting between respective results of the at least two CRC checksums based on the determined value of the switchover condition.

9. The method of claim 8 , wherein one of the CRC checksum calculations is performed using a combination of contents of the CRC field and stuff bits of fields preceding the CRC field, and the stuff bits are not used for another of the CRC checksum calculations.

10. The method of claim 8 , further comprising:
calculating a CRC checksum, wherein, responsive to satisfaction of a condition that the value of the switchover condition meets a predetermined criterion, the calculation of the CRC checksum is performed using a combination of contents of the CRC field and stuff bits of fields preceding the CRC field.

11. The method of claim 1 , further comprising:
determining a value of a second switchover condition;
interpreting the data length code to determine a length of the data field;
wherein the interpretation of the data length code is performed according to an assignment of a combination of all values of the data length code to a first range of lengths if the determined value of the second switchover condition is a first value, and the interpretation of the data length code is performed according to an assignment of a combination of all values of the data length code to a second range of lengths if the determined value of the second switchover condition is a second value, the second range including and being larger than the first range.

12. The method of claim 11 , wherein the largest length of the first range is 8 bytes and the largest length of the second range is greater than 8 bytes.

13. The method of claim 12 , wherein, if the determined value of the second switchover condition is the second value, each possible combination of bits of the data length code is assigned to a different respective data field length than all other combinations of the bits of the data length code.

14. The method of claim 11 , wherein the value of the second switchover condition is one of derived from and set to be consistent with the value of the first switchover condition.

15. The method of claim 11 , wherein the processor is configured to determine the value of the second switchover condition from an identification in at least one of the arbitration field and the control field.

16. The method of claim 11 , wherein, according to the assignments to the first range of lengths and to the second range of lengths, values between 0b0001 and 0b1000 of the data length code are interpreted as respective ones of data field sizes of 1 to 8 bytes, and, according to the assignment to the second range of lengths and not according to the assignment to the first range of lengths, remaining values between 0b1001 and 0b1111 of the data length code are interpreted as respective ones of data field sizes that are greater than 8 bytes.

17. The method of claim 11 , wherein the data length code includes four bits and, if the determined value of the second switchover condition is the second value, the four bits of the data length code are interpreted at least partially in deviation from the CAN standard ISO 11898-1.

18. The method of claim 17 , wherein the processor is configured to determine from at least one of the arbitration field and the control field whether the message is of a first type for which interpretation of the data length code is to be limited to the first range of lengths or is of a second type for which interpretation of the data length code is expandable to the second larger range of lengths depending on the value of the second switchover condition.

19. The method of claim 1 , further comprising:
interpreting the data length code to determine a length of the data field;
wherein the processor is configured to determine from an identification in at least one of the arbitration field and the control field whether the message is of a first type for which interpretation of the data length code is to be limited to a first range of lengths or is of a second type for which interpretation of the data length code is to be expanded to a second larger range of lengths.

20. The method of claim 1 , wherein, as a function of a value of a second switchover condition, different values for bit length in time are assigned to different parts of the obtained message.

21. The method of claim 20 , wherein the bit length in time assigned to a first part of the message is specified at at least a minimum time value, and the bit length in time assigned to a second part of the message is less than the minimum time value.

22. The method of claim 21 , wherein the minimum time value is one microsecond.

23. The method of claim 20 , the different values for bit length in time are implemented by using at least two different scaling factors for setting a bus time unit relative to a smallest time unit or to an oscillator clock pulse in ongoing operation.

24. The method of claim 20 , further comprising:
based on an identification in at least one of the arbitration field and the control field, determining whether the different values for bit length in time are assigned to the message.

Assignees

• Hartwich Florian
• Bosch Gmbh Robert

Inventors

• Hartwich Florian

Classifications

• H04L12/4013

  Management of data rate on the bus (systems modifying transmission characteristics according to link quality H04L1/0001) · CPC title

• H04L12/4135

  using bit-wise arbitration · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• H04L2012/40215

  Controller Area Network CAN · CPC title

• H04L2001/0094

  Bus · CPC title