Processor support for hardware transactional memory

Patent metadata

Field	Value
Publication number	US-9880848-B2
Application number	US-81402510-A
Country	US
Kind code	B2
Filing date	Jun 11, 2010
Priority date	Jun 11, 2010
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

A processing core of a plurality of processing cores is configured to execute a speculative region of code as a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for an issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.

First claim

What is claimed:

1. An apparatus, comprising:
a processing core of a plurality of processing cores, wherein the processing core is configured to:
execute a speculative region of code as a single atomic memory transaction with respect to one or more others of the plurality of processing cores, the speculative region comprising a plurality of program instructions;
add program instructions to corresponding entries of a reorder buffer in response to the program instructions being issued;
set a flag associated with one of the entries in the reorder buffer in response to detecting an abort condition for a corresponding one of the issued program instructions; and
abort execution of the speculative region of the code in response to an entry at a head of the reorder buffer having a set flag indicating a detected abort condition,
wherein the processing core is configured to retire program instructions in the entry at the head of the reorder buffer.

2. The apparatus of claim 1 , wherein the entry that includes the issued program instruction reaches the entry at the head of the reorder buffer in response to all instructions issued before the issued program instruction in program order have been retired.

3. The apparatus of claim 1 , wherein the processing core and at least one other of the plurality of processing cores are on the same chip.

4. The apparatus of claim 1 , wherein execution of the speculative region comprises storing data accessed by one or more instructions of the speculative region in a speculative buffer, wherein the speculative buffer includes at least a primary and secondary buffer.

5. The apparatus of claim 1 , wherein the abort condition for the issued instruction is determined at least in part by determining that the processing core received a cache coherence message indicating a portion of shared memory, wherein execution of the issued instruction comprises accessing the portion of shared memory.

6. The apparatus of claim 1 , wherein the abort condition for the issued instruction is determined at least in part by determining that insufficient capacity exists in a speculative buffer for buffering data accessed by the processing core executing the issued instruction.

7. The apparatus of claim 1 , wherein a beginning of the speculative region is indicated by a pre-defined starting instruction executable by the processing core, and wherein an end of the speculative region is indicated by a pre-defined ending instruction executable by the processing core.

8. The apparatus of claim 7 , wherein the starting and ending instructions are implemented using microinstructions stored by the processing core in a private, read-only memory.

9. The apparatus of claim 1 , wherein the processing core is further configured to:
in response to encountering a branch instruction, record an indication of whether the processing core is executing in a speculative execution mode;
execute one or more instructions in an execution path based at least in part on a predicted outcome of the branch instruction; and
in response to determining that the predicted outcome is incorrect, enter or exit the speculative execution mode based on the recorded indication.

10. A computer-implemented method comprising:
a processing core of a plurality of processing cores performing:
executing a speculative region of code as a single atomic memory transaction with respect one or more others of the plurality of processing cores, the speculative region comprising a plurality of program instructions;
adding program instructions to corresponding entries of a reorder buffer in response to the program instructions being issued;
setting a flag associated with one of the entries in the reorder buffer in response to detecting an abort condition for a corresponding one of the issued program instructions;
aborting execution of the speculative region of the code in response to an entry at a head of the reorder buffer having a set flag indicating a detected abort condition; and
retiring program instructions in the entry at the head of the reorder buffer.

11. The method of claim 10 , wherein an entry reaches the head of the reorder buffer in response to all instructions issued before the issued program instruction in program order being retired.

12. The method of claim 10 , wherein executing the speculative region comprises storing data accessed by one or more instructions of the speculative region in a speculative buffer, wherein the speculative buffer includes at least a primary and secondary buffer.

13. The method of claim 10 , wherein the abort condition for the issued instruction is determined at least in part by determining that the processing core received a cache coherence message indicating a portion of shared memory, wherein execution of the issued instruction comprises accessing the portion of shared memory.

14. The method of claim 10 , wherein the abort condition for the issued instruction is determined at least in part by determining that insufficient capacity exists in a speculative buffer for buffering data accessed by the processing core executing the issued instruction.

15. The method of claim 10 , wherein a beginning of the speculative region is indicated by a pre-defined starting instruction executable by the processing core, and wherein an end of the speculative region is indicated by a pre-defined ending instruction executable by the processing core, wherein the starting and ending instructions are implemented using microinstructions stored by the processing core in a private, read-only memory.

16. The method of claim 10 , further comprising:
in response to encountering a branch instruction, recording an indication of whether the processing core is executing in a speculative execution mode;
executing one or more instructions in an execution path based at least in part on a predicted outcome of the branch instruction; and
in response to determining that the predicted outcome is incorrect, entering or exiting the speculative execution mode based on the recorded indication.

17. A non-transitory computer readable storage medium comprising a data structure which is operated upon by a program executable on a computer system, the program operating on the data structure to perform a portion of a process to fabricate an integrated circuit including circuitry described by the data structure, the circuitry described in the data structure including:
a processing core of a plurality of processing cores, wherein the processing core is configured to:
execute a speculative region of code as a single atomic memory transaction with respect one or more others of the plurality of processing cores, the speculative region comprising a plurality of program instructions;
add program instructions to corresponding entries of a reorder buffer in response to the program instructions being issued;
set a flag associated with one of the entries in the reorder buffer in response to detecting an abort condition for a corresponding one of the issued program instructions;
abort execution of the speculative region of the code in response to an entry at a head of the reorder buffer having a set flag indicating a detected abort condition; and
retire program instructions in the entry at the head of the reorder buffer.

18. The non-transitory computer readable storage medium of claim 17 , wherein the storage medium stores at least one of HDL, Verilog, or GDSII data.

Assignees

• Chung Jaewoong
• Christie David S
• Hohmuth Michael P
• Diestelhorst Stephan
• Pohlack Martin T
• Yen Luke
• Advanced Micro Devices Inc

Inventors

• Chung Jaewoong
• Christie David S
• Hohmuth Michael P
• Diestelhorst Stephan
• Pohlack Martin T
• Yen Luke

Classifications

• G06F9/467

  Transactional memory (G06F9/528 takes precedence) · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F9/30087

  Synchronisation or serialisation instructions · CPC title

• G06F9/3842 Primary

  Speculative instruction execution · CPC title

• G06F9/3857

  Physics · mapped topic