Power management mechanism

Patent metadata

Field	Value
Publication number	US-9880596-B2
Application number	US-201213536819-A
Country	US
Kind code	B2
Filing date	Jun 28, 2012
Priority date	Feb 17, 2010
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

An integrated circuit includes a global power supply node. A first power domain has a first power management circuit, which includes a local power supply node. A first power control circuit is capable of receiving an input signal. A second power control circuit has a higher current capacity than the first power control circuit. The first power control circuit and the second power control circuit are coupled to the local power supply node and the global power supply node. The input signal is configured to initiate a power sequence, e.g., a power up process or a power down process, in the first power control circuit. A first control signal generated by the first power control circuit is configured to initiate a power sequence in the second power control circuit.

First claim

What is claimed is:

1. A circuit, comprising:
a global power supply node; and
a first local power supply node;
a first power control circuit configured to enable a first current path between the global power supply node and the first local power supply node in response to an input signal;
a first sequence circuit configured to generate a first control signal in response to a voltage level of the first local power supply node; and
a second power control circuit configured to enable a second current path between the global power supply node and the first local power supply node in response to the first control signal, and current capacity of the second current path being greater than current capacity of the first current path.

2. The circuit of claim 1 , wherein the first power control circuit comprises:
a first transistor having a gate terminal, a source terminal, and a drain terminal, the source terminal and the drain terminal of the first transistor each coupled to a corresponding one of the global power supply node and the first local power supply node.

3. The circuit of claim 2 , wherein the first power control circuit further comprises:
a second transistor coupled to the gate terminal of the first transistor and configured to cause the first transistor functioning as a diode in response to the input signal.

4. The circuit of claim 1 , wherein the second power control circuit comprises:
a third transistor having a gate terminal, a source terminal, and a drain terminal, the source terminal and the drain terminal of the third transistor each coupled to a corresponding one of the global power supply node and the first local power supply node, and the gate terminal of the third transistor is configured to receive the first control signal.

5. The circuit of claim 1 , wherein the first sequence circuit comprises:
an inverting circuit configured to generate the first control signal in response to the input signal; and
a fourth transistor configured to enable the inverting circuit in response to the voltage level of the first local power supply node.

6. The circuit of claim 5 , wherein the inverting circuit comprises:
an output node;
a fifth transistor having a gate terminal, a source terminal, and a drain terminal, the source terminal of the fifth transistor coupled to the global power supply node; and
a sixth transistor having a gate terminal, a source terminal, and a drain terminal, the source terminal of the sixth transistor coupled to the fourth transistor, the drain terminal of the sixth transistor coupled to the drain terminal of the fifth transistor at the output node of the inverting circuit, the gate terminal of the six transistor coupled to the gate terminal of the fifth transistor, and the first control signal being generated at the output node of the inverting circuit.

7. The circuit of claim 1 , further comprising:
a second local power supply node; and
a third power control circuit configured to enable a third current path between the global power supply node and the second local power supply node in response to the first control signal.

8. The circuit of claim 7 , wherein the third power control circuit comprises:
a seventh transistor having a gate terminal, a source terminal, and a drain terminal, the source terminal and the drain terminal of the seventh transistor each coupled to a corresponding one of the global power supply node and the second local power supply node.

9. The circuit of claim 8 , wherein the third power control circuit further comprises:
an eighth transistor coupled to the gate terminal of the seventh transistor and configured to cause the seventh transistor functioning as a diode in response to the first control signal.

10. The circuit of claim 7 , further comprising:
a second sequence circuit configured to generate a second control signal in response to a voltage level of the second local power supply node; and
a fourth power control circuit configured to enable a fourth current path between the global power supply node and the second local power supply node in response to the second control signal, and current capacity of the fourth current path being greater than current capacity of the third current path.

11. The circuit of claim 10 , wherein the fourth power control circuit comprises:
a ninth transistor having a gate terminal, a source terminal, and a drain terminal, the source terminal and the drain terminal of the ninth transistor each coupled to a corresponding one of the global power supply node and the second local power supply node, and the gate terminal of the ninth transistor is configured to receive the second control signal.

12. A circuit, comprising:
a global power supply node; and
a first local power supply node;
a first transistor having a gate terminal, a source terminal, and a drain terminal, the source terminal and the drain terminal of the first transistor each coupled to a corresponding one of the global power supply node and the first local power supply node;
a second transistor having a gate terminal, a source terminal, and a drain terminal, the drain terminal of the second transistor coupled to the first local power supply node, the source terminal of the second transistor coupled to the gate terminal of the first transistor;
a third transistor having a gate terminal, a source terminal, and a drain terminal, the source terminal of the third transistor coupled to the global power supply node, and the drain terminal of the third transistor coupled to the source terminal of the second transistor; and
an inverter having an input and an output, the input of the inverter coupled to the gate terminal of the second transistor, and the output of the inverter coupled to the gate terminal of the third transistor.

13. The circuit of claim 12 , wherein the circuit satisfies one of the following two conditions:
(1) the first, second, and third transistors are all P-type transistors; and
(2) the first, second, and third transistors are all N-type transistors.

14. The circuit of claim 12 , further comprising:
a fourth transistor having a gate terminal, a source terminal, and a drain terminal, the source terminal of the fourth transistor coupled to the global power supply node, and the gate terminal of the fourth transistor coupled to the gate terminal of the third transistor;
a fifth transistor having a gate terminal, a source terminal, and a drain terminal, the drain terminal of the fifth transistor coupled to the drain terminal of the fourth transistor, and the gate terminal of the fifth transistor coupled to the gate terminal of the third transistor; and
a sixth transistor having a gate terminal, a source terminal, and a drain terminal, the drain terminal of the sixth transistor coupled to the source terminal of the fifth transistor, and the gate terminal of the sixth transistor coupled to the first local power supply node.

15. The circuit of claim 14 , further comprising:
a seventh transistor having a gate terminal, a source terminal, and a drain terminal, the source terminal and the drain terminal of the seventh transistor each coupled to a corresponding one of the global power supply node and the first local power supply node, and the gate terminal of the seventh transistor coupled to the drain terminals of the fourth and fifth transistors.

16. The circuit of claim 14 , further comprising:
a second local power supply node;
an eighth transistor having a source terminal and a drain terminal each coupled to a corresponding one of the global power supply node and the second local power supply node, the e

Assignees

• Cheng Hank
• Upputuri Bharath
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Hank
• Upputuri Bharath

Classifications

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• H02M3/335

  using semiconductor devices only · CPC title

• Y10T307/406

  Cross-Sectional Technologies · mapped topic

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title