Loopback techniques for synchronization of oscillator signal in radar

Patent metadata

Field	Value
Publication number	US-9880261-B2
Application number	US-201414503181-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	Sep 30, 2014
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

The disclosure provides a radar apparatus for estimating a position and a velocity of a plurality of obstacles. The radar apparatus includes a slave radar chip. A master radar chip is coupled to the slave radar chip. The master radar chip includes a local oscillator that generates a transmit signal. The slave radar chip receives the transmit signal on a first path and sends the transmit signal back to the master radar chip on a second path. A delay detect circuit is coupled to the local oscillator and receives the transmit signal from the slave radar chip on the second path and the transmit signal from the local oscillator. The delay detect circuit estimates a routing delay from the transmit signal received from the slave radar chip on the second path and from the transmit signal received from the local oscillator.

First claim

What is claimed is:

1. A radar apparatus comprising:
a slave radar chip;
a master radar chip coupled to the slave radar chip, the master radar chip comprising:
a local oscillator configured to generate a transmit signal, wherein the slave radar chip is configured to receive the transmit signal on a first path and configured to send the transmit signal back to the master radar chip on a second path; and
a delay detect circuit coupled to the local oscillator and configured to receive the transmit signal from the slave radar chip on the second path and the transmit signal from the local oscillator, the delay detect circuit configured to estimate a routing delay from the transmit signal received from the slave radar chip on the second path and from the transmit signal received from the local oscillator.

2. The radar apparatus of claim 1 , wherein the master radar chip further comprises:
a multiplexer coupled to the local oscillator and configured to receive the transmit signal from the local oscillator and configured to send the transmit signal to the slave radar chip on the first path; and
one or more transceiver units coupled to the multiplexer, wherein the multiplexer is configured to provide the transmit signal to the one or more transceiver units.

3. The radar apparatus of claim 1 , wherein the slave radar chip comprises:
a multiplexer coupled to a local oscillator, the multiplexer configured to receive the transmit signal on the first path and configured to send the transmit signal on the second path;
a delay detect circuit coupled to the multiplexer and the local oscillator; and
one or more transceiver units coupled to the multiplexer, wherein the multiplexer is configured to provide the transmit signal to the one or more transceiver units.

4. The radar apparatus of claim 1 , wherein a path from the multiplexer in the master radar chip to the multiplexer in the slave radar chip is the first path and a path from the multiplexer in the slave radar chip to the multiplexer in the master radar chip is the second path.

5. The radar apparatus of claim 1 , wherein a length of the first path is equal to a length of the second path.

6. The radar apparatus of claim 1 , wherein the transceiver unit comprises at least one of a transmit unit and a receive unit.

7. The radar apparatus of claim 6 , wherein the transmit unit comprises:
a power amplifier coupled to the multiplexer and configured to amplify the transmit signal; and
a transmit antenna unit coupled to the power amplifier and configured to transmit the transmit signal received from the power amplifier, wherein the transmit signal is scattered by the plurality of obstacle to generate a scattered signal.

8. The radar apparatus of claim 6 , wherein the receive unit comprises:
a receive antenna unit configured to receive the scattered signal;
a low-noise amplifier (LNA) coupled to the receive antenna unit and configured to amplify the scattered signal;
a mixer coupled to the LNA and the multiplexer, the mixer configured to mix the scattered signal and the transmit signal to generate an IF (intermediate frequency) signal;
an ADC (analog to digital converter) coupled to the mixer and configured to sample the IF signal to generate a sampled data; and
a digital signal processor (DSP) coupled to the ADC and the delay detect circuit in the master radar chip, the DSP configured to estimate a position and a velocity of the plurality of obstacles from the sampled data and the routing delay.

9. The radar apparatus of claim 1 further comprising a plurality of radar chips and one or more radar chips of the plurality of radar chips are configured as master radar chips and one or more radar chips of the plurality of radar chips are configured as slave radar chips.

10. The radar apparatus of claim 9 , wherein each radar chip of the plurality of radar chips comprises the one or more transceiver units and the local oscillator integrated on a single chip.

11. A radar apparatus comprising:
a slave radar chip;
a master radar chip coupled to the slave radar chip, the master radar chip comprising a local oscillator configured to generate a transmit signal, wherein the slave radar chip is configured to receive the transmit signal on a first path from the master radar chip; and
an external path coupled to the master radar chip and configured to receive the transmit signal from the master radar chip and provide the transmit signal back to the master radar chip.

12. The radar apparatus of claim 11 , wherein a routing delay of the first path is equal to a routing delay on the external path.

13. The radar apparatus of claim 11 , wherein the master radar chip comprises:
a multiplexer coupled to the local oscillator and configured to receive the transmit signal from the local oscillator and configured to send the transmit signal to the slave radar chip on the first path and the external path, the multiplexer configured to receive the transmit signal from the external path; and
one or more transceiver units coupled to the multiplexer, wherein the multiplexer is configured to provide the transmit signal received from the external path to the one or more transceiver units.

14. The radar apparatus of claim 11 , wherein the slave radar chip comprises:
a multiplexer coupled to a local oscillator, the multiplexer configured to receive the transmit signal on the first path; and
one or more transceiver units coupled to the multiplexer, wherein the multiplexer is configured to provide the transmit signal received on the first path to the one or more transceiver units.

15. The radar apparatus of claim 11 , wherein a path from the multiplexer in the master radar chip to the multiplexer in the slave radar chip is the first path.

16. The radar apparatus of claim 11 , wherein the transceiver unit comprises at least one of a transmit unit and a receive unit.

17. The radar apparatus of claim 16 , wherein the transmit unit comprises:
a power amplifier coupled to the multiplexer and configured to amplify the transmit signal; and
a transmit antenna unit coupled to the power amplifier and configured to transmit the transmit signal received from the power amplifier, wherein the transmit signal is scattered by the plurality of obstacle to generate a scattered signal.

18. The radar apparatus of claim 16 , wherein the receive unit comprises:
a receive antenna unit configured to receive the scattered signal;
a low-noise amplifier (LNA) coupled to the receive antenna unit and configured to amplify the scattered signal;
a mixer coupled to the LNA and the multiplexer, the mixer configured to mix the scattered signal and the transmit signal to generate an IF (intermediate frequency) signal;
an ADC (analog to digital converter) coupled to the mixer and configured to sample the IF signal to generate a sampled data; and
a digital signal processor (DSP) coupled to the ADC and configured to estimate a position and a velocity of the plurality of obstacles from the sampled data.

19. The radar apparatus of claim 11 further comprising a plurality of radar chips and one or more radar chips of the plurality of radar chips are configured as master radar chips and one or more radar chips of the plurality of radar chips are configured as slave radar chips.

20. The radar apparatus of claim 19 , wherein each radar chip of the plurality of radar chips comprises the one or more transceiver units and the local oscillator integrated on a single chip.

21. A radar apparatus comprising:
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Assignees

• Texas Instruments Inc

Inventors

• Subburaj Karthik
• Ginsburg Brian
• Ramasubramanian Karthik

Classifications

• G01S7/032 Primary

  Constructional details for solid-state radar subsystems · CPC title

• G01S13/87

  Combinations of radar systems, e.g. primary radar and secondary radar · CPC title

• G01S7/036

  involving a transfer mixer · CPC title

• G01S13/931

  of land vehicles · CPC title

• H04L7/04

  Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)} · CPC title