Capacitive passive mixer baseband receiver with broadband harmonic rejection

Patent metadata

Field	Value
Publication number	US-9876518-B2
Application number	US-201615273536-A
Country	US
Kind code	B2
Filing date	Sep 22, 2016
Priority date	Sep 22, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

Systems, methods, and articles of manufacture, including computer program products, are provided for capacitive passive mixer baseband receivers with broadband harmonic rejection. In some embodiments, an apparatus is provided. The apparatus includes a receiver configured to receive an input signal and generate, based on the input signal, an in-phase portion and a quadrature phase portion. The apparatus further includes a harmonic rejection mixer comprising a plurality of capacitors, the plurality of capacitors encoded with a plurality of capacitance values, the harmonic rejection mixer configured to reduce harmonics in the input signal based on applying a quantity of the plurality of capacitance values to the input signal. The apparatus further includes a plurality of switches configured to activate the plurality of capacitors, the quantity of the plurality of predetermined capacitance values applied to the input signal based on a quantity of the plurality of capacitors that are active.

First claim

What is claimed is:

1. An apparatus, comprising:
a receiver configured to receive an input signal, wherein the receiver is further configured to generate, based on the input signal, an in-phase portion and a quadrature phase portion;
a harmonic rejection mixer comprising a plurality of capacitors, wherein the plurality of capacitors are encoded with a plurality of predetermined capacitance values, wherein the harmonic rejection mixer is configured to reduce harmonics in the input signal, and wherein the reduction is based on applying a quantity of the plurality of predetermined capacitance values to the input signal; and
a plurality of switches configured to activate the plurality of capacitors, wherein the quantity of the plurality of predetermined capacitance values applied to the input signal is based on a quantity of the plurality of capacitors that are active.

2. The apparatus of claim 1 , further comprising:
a multi-phase local oscillator clock, wherein the plurality of switches activate the plurality of capacitors based on signals from the multi-phase local oscillator clock.

3. The apparatus of claim 2 , wherein the plurality of switches are sequentially opened or closed based on the signals from the multi-phase local oscillator clock.

4. The apparatus of claim 1 , wherein the predetermined capacitance values are based upon a capacitance of a corresponding capacitor from the plurality of capacitors.

5. The apparatus of claim 4 , wherein at least a portion of the plurality of capacitors have different predetermined capacitance values.

6. The apparatus of claim 1 , wherein the plurality of capacitors include a first set of capacitors and a second set of capacitors, wherein the first set of capacitors are configured to generate a cosine waveform based on the in-phase portion, wherein the second set of capacitors are configured to generate a sine waveform based on the quadrature phase portion, and wherein the harmonic rejection mixer is configured to combine the cosine waveform and the sine waveform.

7. The apparatus of claim 6 , wherein combining the cosine waveform and the sine waveform provides a weighted signal based on the input signal, wherein the weighted signal comprises a signal that is downconverted from the received input signal, and wherein generating the weighted signal reduces a strength of an undesired signal present in the input signal.

8. The apparatus of claim 6 , wherein the harmonic rejection mixer further includes a first amplifier configured to amplify the combined cosine waveform and sine waveform.

9. The apparatus of claim 1 , further comprising:
a multiple input multiple output analog core configured to separate a first signal from the input signal and a second signal from the input signal.

10. A method, comprising:
receiving an input signal;
generating, based on the input signal, an in-phase portion and a quadrature phase portion;
activating a quantity of a plurality of capacitors; and
reducing, via a harmonic rejection mixer comprising the plurality of capacitors, harmonics in the input signal, wherein the plurality of capacitors are encoded with a plurality of predetermined capacitance values, wherein the reducing is based on applying a quantity of the plurality of predetermined capacitance values to the input signal, and wherein the quantity of the plurality of predetermined capacitance values applied to the input signal is based on the quantity of the plurality of capacitors that are active.

11. The method of claim 10 , wherein the plurality of capacitors are activated based on signals from a multi-phase local oscillator clock, wherein a plurality of switches are sequentially opened or closed based on the signals from the multi-phase local oscillator clock.

12. The method of claim 10 , wherein the predetermined capacitance values are based upon a capacitance of a corresponding capacitor from the plurality of capacitors, and wherein at least a portion of the plurality of capacitors have different predetermined capacitance values.

13. The method of claim 10 , wherein the applying further comprises:
generating, via a first set of capacitors of the plurality of capacitors, a cosine waveform based on the in-phase portion;
generating, via a second set of capacitors of the plurality of capacitors, a sine waveform based on the quadrature phase portion; and
combining the cosine waveform and the sine waveform to provide a weighted signal based on the input signal, wherein the weighted signal comprises a signal that is downconverted from the received input signal.

14. The method of claim 10 , further comprising:
separating, via a multiple input multiple output analog core, a first signal from the input signal and a second signal from the input signal.

15. A computer program product comprising a non-transitory machine-readable medium storing instructions that, when executed by at least one programmable processor, cause the at least one programmable processor to perform operations comprising:
generating, based on the input signal, an in-phase portion and a quadrature phase portion;
activating a quantity of a plurality of capacitors; and
reducing, via a harmonic rejection mixer comprising the plurality of capacitors, harmonics in the input signal, wherein the plurality of capacitors are encoded with a plurality of predetermined capacitance values, wherein the reducing is based on applying a quantity of the plurality of predetermined capacitance values to the input signal, and wherein the quantity of the plurality of predetermined capacitance values applied to the input signal is based on the quantity of the plurality of capacitors that are active.

16. The computer program product of claim 15 , wherein the plurality of capacitors are activated based on signals from a multi-phase local oscillator clock, wherein a plurality of switches are sequentially opened or closed based on the signals from the multi-phase local oscillator clock.

17. The computer program product of claim 15 , wherein the predetermined capacitance values are based upon a capacitance of a corresponding capacitor from the plurality of capacitors, and wherein at least a portion of the plurality of capacitors have different predetermined capacitance values.

18. The computer program product of claim 15 , wherein the applying further comprises:
generating, via a first set of capacitors of the plurality of capacitors, a cosine waveform based on the in-phase portion;
generating, via a second set of capacitors of the plurality of capacitors, a sine waveform based on the quadrature phase portion; and
combining the cosine waveform and the sine waveform to provide a weighted signal based on the input signal, wherein the weighted signal comprises a signal that is downconverted from the received input signal.

19. The computer program product of claim 15 , wherein the operations further comprise:
separating, via a multiple input multiple output analog core, a first signal from the input signal and a second signal from the input signal.

Assignees

• Univ California

Inventors

• Kim Chul
• Thomas Chris Michael
• Cauwenberghs Gert
• Larson Lawrence E
• Joshi Siddharth
• Ha Sohmyung

Classifications

• H04L27/22

  Demodulator circuits; Receiver circuits · CPC title

• H03H7/0138

  Electrical filters or coupling circuits · CPC title

• H04B1/16 Primary

  Circuits · CPC title

• H04L27/2276

  using frequency multiplication or harmonic tracking · CPC title