Semiconductor device including sense insulated-gate bipolar transistor

Patent metadata

Field	Value
Publication number	US-9876092-B2
Application number	US-201715585492-A
Country	US
Kind code	B2
Filing date	May 3, 2017
Priority date	May 12, 2014
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor layer including a main insulated-gate bipolar transistor (IGBT) cell and a sense insulated-gate bipolar transistor (IGBT) cell connected in parallel to each other;
a first resistance portion having a first resistance value and a second resistance portion having a second resistance value higher than the first resistance value, the first resistance portion and the second resistance portion being connected between a gate wiring portion of the sense IGBT cell and a gate wiring portion of the main IGBT cell by using a first channel and a second channel, respectively, the first channel and the second channel being different channels from each other;
a first diode provided in the first channel;
a second diode provided in the second channel in a manner oriented reversely to the first diode;
an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell; and
a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.

2. The semiconductor device according to claim 1 , wherein the gate wiring portion of the sense IGBT cell includes a gate electrode formed with a predetermined wiring pattern to divide the sense IGBT cell into respective cell units, and
the first resistance portion and the second resistance portion are disposed on peripheral edge portions of the gate electrode, respectively.

3. The semiconductor device according to claim 2 , wherein the gate electrode includes a striped pattern, and
the first resistance portion and the second resistance portion are disposed on one end portion of the gate electrode in the striped pattern and the other end portion on a side opposite to the one end portion, respectively.

4. The semiconductor device according to claim 1 , wherein the first resistance portion has a short wiring length compared to that of the second resistance portion.

5. The semiconductor device according to claim 1 , wherein the first resistance portion has a wide wiring width compared to that of the second resistance portion.

6. The semiconductor device according to claim 1 , wherein the first diode is formed of a first deposition layer disposed on the semiconductor layer, having a central portion of a first conductivity type and a peripheral edge portion of a second conductivity type enclosing the central portion, and
the second diode is formed of a second deposition layer disposed on the semiconductor layer, having a central portion of a first conductivity type and a peripheral edge portion of a second conductivity type enclosing the central portion.

7. The semiconductor device according to claim 6 , wherein any one or both of the peripheral edge portion of the first deposition layer and the peripheral edge portion of the second deposition layer are formed so as to enclose an entire circumference of the central portion inside thereof, respectively.

8. The semiconductor device according to claim 6 , wherein any one or both of the peripheral edge portion of the first deposition layer and the peripheral edge portion of the second deposition layer are formed so as to selectively enclose a part of the central portion inside thereof, respectively.

9. The semiconductor device according to claim 6 , wherein any one or both of the first deposition layer and the second deposition layer is made of doped polysilicon.

10. The semiconductor device according to claim 6 , wherein the gate wiring is connected to the central portion of the first deposition layer and the peripheral edge portion of the second deposition layer, and
the semiconductor device includes a first contact wiring that connects the peripheral edge portion of the first deposition layer and the first resistance portion and a second contact wiring that connects the central portion of the second deposition layer and the second resistance portion.

11. The semiconductor device according to claim 6 , wherein the first resistance portion and the second resistance portion are formed using a deposition layer that is the same as the first deposition layer and the second deposition layer.

12. The semiconductor device according to claim 1 , wherein the gate wiring includes a main line portion and a first branching portion and a second branching portion branching off the main line portion, and
the first branching portion and the second branching portion are connected to the first diode and the second diode, respectively.

13. The semiconductor device according to claim 1 , comprising a collector electrode disposed on a back surface of the semiconductor layer, being common between the main IGBT cell and the sense IGBT cell.

Assignees

• Rohm Co Ltd

Inventors

• Hikasa Akihiro

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title