Method of manufacturing a device with MOS transistors

Patent metadata

Field	Value
Publication number	US-9876032-B2
Application number	US-201615296205-A
Country	US
Kind code	B2
Filing date	Oct 18, 2016
Priority date	Oct 22, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.

First claim

The invention claimed is:

1. A method of manufacturing a device comprising low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors, of a first type and of a second type, comprising the successive steps of:
a) forming gate stacks of the LV and HV MOS transistors over a semiconductor layer;
b) forming first spacers by depositing a first layer of a first insulating material;
c) forming second spacers of a second insulating material different from the first insulating material;
d) removing the second spacers from the LV MOS transistors;
e) at the location of each transistor of the first type, etching the first layer all the way to the semiconductor layer while leaving in place only the first spacer on the gate stack of the LV MOS transistor of the first type and leaving in place both the first and second spacers on the gate stack of the HV MOS transistor of the first type;
f) growing a first doped semiconductor material of a first conductivity type from an exposed surface of the semiconductor layer at the location of each transistor of the first type;
g) depositing a second layer of the first insulating material on the gate stacks of the LV and HV MOS transistors of the second type;
h) at the location of each transistor of the second type, etching the first and second layers all the way to the semiconductor layer while leaving in place the second layer and the first and second spacers on the gate stack of the HV MOS transistor of the second type and leaving in place the second layer and the first spacer on the gate stack of the HV MOS transistor of the second type; and
i) growing a second doped semiconductor material of a second conductivity type from the exposed surface of the semiconductor layer at the location of each transistor of the second type.

2. The method of claim 1 , wherein step c) comprises depositing a layer of the second material, and removing by etching the layer of the second material while leaving in place the second spacers.

3. The method of claim 1 , wherein a gate insulator of the gate stack of the LV MOS transistors has an equivalent thickness smaller than an equivalent thickness of a gate insulator of the gate stack of the HV MOS transistors.

4. The method of claim 1 , wherein the semiconductor layer rests on an insulator and a thickness of the semiconductor layer is smaller than 20 nm.

5. The method of claim 1 , wherein the first insulating material is silicon nitride and the second insulating material is silicon oxide.

6. The method of claim 1 , wherein the transistors of the first type are NMOS and the transistors of the second type are PMOS.

7. The method of claim 1 , wherein each of the first and second semiconductor materials is selected from a group consisting of: silicon, germanium, silicon carbide, and silicon-germanium.

8. A device comprising low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of a first type and of a second type, comprising:
a gate stack of each transistor on a semiconductor layer;
source and drain regions of each transistor of the first type comprising a first doped semiconductor material of a first conductivity type laterally bordering the gate stack of the transistor;
source and drain regions of each transistor of the second type comprising a second doped semiconductor material of a second conductivity type laterally bordering the gate stack of the transistor; and
spacers on the gate stacks of the transistors, said spacers comprising:
first spacers consisting of a first insulating material layer on the gate stacks of the LV MOS transistors of the first type;
second spacers consisting made of the first insulating material layer and a second insulating material layer different from the first insulating material layer on gate stacks of the HV MOS transistors of the first type;
third spacers consisting of the first insulating material layer, the second insulating material layer and a third insulating material layer made of a same material as the first insulating material layer on gate stacks of the HV MOS transistors of the second type; and
fourth spacers consisting of the first insulating material layer and the third insulating material layer on gate stacks of the LV MOS transistors of the second type.

9. The device of claim 8 , wherein the first and third insulating material layers join on the side of the semiconductor layer to form a U-shape with the second insulating material layer positioned between the first insulating material layer and the third insulating material layer.

10. The device of claim 8 , wherein a gate insulator of the gate stack of the LV MOS transistors has an equivalent thickness smaller than an equivalent thickness of a gate insulator of the gate stack of the HV MOS transistors.

11. The device of claim 8 , wherein the semiconductor layer rests on an insulator and a thickness of the semiconductor layer is smaller than 20 nm.

12. The device of claim 8 , wherein the first insulating material layer is made of silicon nitride and the second insulating material layer is made of silicon oxide.

13. The device of claim 8 , wherein the transistors of the first type are NMOS and wherein the transistors of the second type are PMOS.

14. The device of claim 8 , wherein each of the first and second semiconductor material layers are made from materials selected from the group consisting of: silicon, germanium, silicon carbide, and silicon-germanium.

15. A method of manufacturing a device comprising a low-voltage (LV) metal oxide semiconductor (MOS) transistor and a high-voltage (HV) MOS transistor, comprising the successive steps of:
forming gate stacks of the LV and HV MOS transistors over a semiconductor layer;
depositing a first layer of a first insulating material;
depositing a second layer of a second insulating material;
forming first spacers made from the first layer of the first insulating material on sidewalls of the gate stack of the LV MOS transistor and on sidewalls of the gate stack of the HV MOS transistor;
forming second spacers made from the second layer of the second insulating material on sidewalls of the first spacers of the HV MOS transistor, but not on sidewalls of the first spacers of the LV MOS transistor;
depositing a third layer of a third insulating material;
forming third spacers made from the third layer of the third insulating material on sidewalls of the first spacers of the LV MOS transistor and on sidewalls of the second spacers of the HV MOS transistor; and
epitaxially growing raised source and drain regions from the semiconductor layer for each of the LV and HV MOS transistors, said raised source and drain region separated from the gate stack of the LV MOS transistor by the third spacers, and said raised source and drain region separated from the gate stack of the HV MOS transistor by the fourth spacers.

16. The method of claim 15 , wherein the first and third insulating materials are a same insulating material.

17. The method of claim 15 , wherein forming first spacers on sidewalls of the gate stack of the LV MOS transistor comprises removing the second layer and forming the first layer into said first spacers.

18. The method of claim 15 , wherein the LV and HV MOS transistors are p-channel transistors.

Assignees

• St Microelectronics Crolles 2 Sas
• Commissariat Energie Atomique

Inventors

• Chhun Sonarith
• Josse Emmanuel
• Bidal Gregory
• Golanski Dominique
• Andrieu Francois
• Mazurier Jerome
• Weber Olivier

Classifications

• H10P50/644

  Anisotropic liquid etching (H10P50/61 takes precedence) · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3408

  Silicon carbide · CPC title