Method for integrating a light emitting device

US9876000B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9876000-B2
Application numberUS-201715405060-A
CountryUS
Kind codeB2
Filing dateJan 12, 2017
Priority dateJun 17, 2013
Publication dateJan 23, 2018
Grant dateJan 23, 2018

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Light emitting devices and methods of integrating micro LED devices into light emitting device are described. In an embodiment a light emitting device includes a reflective bank structure within a bank layer, and a conductive line atop the bank layer and elevated above the reflective bank structure. A micro LED device is within the reflective bank structure and a passivation layer is over the bank layer and laterally around the micro LED device within the reflective bank structure. A portion of the micro LED device and a conductive line atop the bank layer protrude above a top surface of the passivation layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A light emitting device comprising: a substrate; a bank layer over the substrate, the bank layer including a sidewall; a bottom electrode layer on the substrate, and running along the sidewall of the bank layer and atop the bank layer; an LED device bonded to the bottom electrode layer; a conductive line atop the bank layer; a passivation layer spanning over the substrate and the bank layer, the passivation layer laterally surrounding the LED device and including a top surface; a first recess in the top surface of the passivation layer that exposes the conductive line atop the bank layer; and a top electrode layer that spans directly over the LED device, the passivation layer, and within the first recess in the passivation layer such that the top electrode layer is in electrical contact with the conductive line atop the bank layer. 2. The light emitting device of claim 1 , further comprising a second recess in the top surface of the passivation layer that exposes the LED device, wherein the top electrode layer spans within the second recess in the passivation layer such that the top electrode layer is in electrical contact with the LED device. 3. The light emitting device of claim 2 , wherein the passivation layer comprises a thermoset material. 4. The light emitting device of claim 3 , wherein the thermoset material is an acrylic. 5. The light emitting device of claim 2 , wherein the LED device comprises p-n diode between a bottom contact and a top contact. 6. The light emitting device of claim 5 , wherein the LED device further comprises an LED bonding layer below the bottom contact. 7. The light emitting device of claim 6 , wherein the LED bonding layer is diffused with a substrate bonding layer on the bottom electrode layer to form an inter-metallic compound. 8. The light emitting device of claim 7 , wherein the LED bonding layer is characterized by a higher liquidus temperature than the substrate bonding layer, and the intermetallic compound is characterized by a higher liquidus temperature than both the LED bonding layer and the substrate bonding layer. 9. The light emitting device of claim 5 , further comprising a dielectric barrier layer along sidewalls of the p-n diode. 10. The light emitting device of claim 2 , further comprising an integrated circuit interconnected with the bottom electrode layer. 11. The light emitting device of claim 10 , wherein the substrate is a thin film transistor substrate. 12. The light emitting device of claim 2 , wherein the bottom electrode layer comprises a reflective metallic film. 13. The light emitting device of claim 2 , wherein the bottom electrode layer and the conductive line are formed of a same metallic film. 14. The light emitting device of claim 2 , further comprising a cover layer over the top electrode layer. 15. The light emitting device of claim 14 , wherein the cover layer is a conformal layer. 16. The light emitting device of claim 15 , wherein the cover layer is transparent. 17. The light emitting device of claim 2 , wherein the conductive line is a Vss line. 18. The light emitting device of claim 2 , wherein the bank layer comprises metal oxide particles. 19. The light emitting device of claim 2 , wherein the light emitting device is a display panel in a display system. 20. The light emitting device of claim 2 , wherein the light emitting device is a light source in a lighting system.

Assignees

Inventors

Classifications

  • batch processes · CPC title

  • H10W90/00Primary

    Package configurations · CPC title

  • Connection of the pixel electrodes to the driving transistors · CPC title

  • Interconnections, e.g. wiring lines or terminals (connection of the pixel electrodes to the driving transistors H10H29/39) · CPC title

  • Interconnections (of active-matrix LED displays H10H29/49) · CPC title

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Frequently asked questions

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What does patent US9876000B2 cover?
Light emitting devices and methods of integrating micro LED devices into light emitting device are described. In an embodiment a light emitting device includes a reflective bank structure within a bank layer, and a conductive line atop the bank layer and elevated above the reflective bank structure. A micro LED device is within the reflective bank structure and a passivation layer is over the b…
Who is the assignee on this patent?
Apple Inc, Apple Inc
What technology area does this patent fall under?
Primary CPC classification H10W72/0198. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 23 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).