Circuit and display device

Patent metadata

Field	Value
Publication number	US-9875727-B2
Application number	US-201414500126-A
Country	US
Kind code	B2
Filing date	Sep 29, 2014
Priority date	May 29, 2014
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A circuit arranged in a gate drive area on a display panel comprises control lines. Each control line is connected with multiple gate lines, and the gate lines connected with each control line are distributed at intervals on the display panel. A switch-on level can be provided sequentially to the control lines in a preset time interval when the display panel is being shut down. The circuit mitigates or otherwise eliminates a shutdown afterimage phenomenon and also avoids delivery of a relatively large instantaneous current generated at shutdown.

First claim

The invention claimed is:

1. A circuit arranged in a gate drive area on a display panel, the circuit comprising: a plurality of control lines,
wherein each of the plurality of control lines is connected with a plurality of gate lines, and the plurality of gate lines connected with each control line are distributed at intervals on the display panel, and adjacent gate lines in the plurality of gate lines are spaced by gate lines connected with other control lines in the plurality of control lines,
wherein a switch-on level is provided sequentially to the plurality of control lines in a preset time interval when the display panel is shut down, such that the gate lines connected with the control line which is provided with the switch-on level are switched on, and
wherein each of the plurality of gate lines is connected with a respective control line by a switch transistor, wherein the gate of the switch transistor is connected with the respective control line, a source of the switch transistor is directly connected with the gate line, and a drain of the switch transistor is directly connected with a transistor turn-on voltage input terminal, and wherein the transistor turn-on voltage input terminal is different from the respective control line and is not directly connected with the respective control line.

2. The circuit as claimed in claim 1 , wherein the number of the plurality of control lines is three, and wherein adjacent gate lines in the plurality of gate lines are spaced by two gate lines connected with other control lines in the plurality of control lines.

3. The circuit as claimed in claim 1 , wherein the number of the plurality of control lines is greater than three.

4. The circuit as claimed in claim 1 , comprising a plurality of switch transistors, wherein the drain of each of the plurality of switch transistors is input with the same transistor turn-on voltage.

5. A display device comprising: a display panel,
wherein a gate drive area of the display panel comprises a circuit, the circuit comprises a plurality of control lines,
wherein each of the plurality of control lines is connected with a plurality of gate lines, and the plurality of gate lines connected with each control line are distributed at intervals on the display panel, and adjacent gate lines in the plurality of gate lines are spaced by gate lines connected with other control lines in the plurality of control lines,
wherein a switch-on level is provided sequentially to the plurality of control lines in a preset time interval when the display panel is shut down, such that the gate lines connected with the control line which is provided with the switch-on level are switched on, and
wherein each of the plurality of gate lines is connected with a respective control line by a switch transistor, wherein the gate of the switch transistor is connected with the respective control line, a source of the switch transistor is directly connected with the gate line, and a drain of the switch transistor is directly connected with a transistor turn-on voltage input terminal, and wherein the transistor turn-on voltage input terminal is different from the respective control line and is not directly connected with the respective control line.

6. The display device as claimed in claim 5 , wherein the number of the plurality of control lines is three, and wherein adjacent gate lines in the plurality of gate lines are spaced by two gate lines connected with other control lines in the plurality of control lines.

7. The display device as claimed in claim 5 , wherein the number of the plurality of control lines is greater than three.

8. The display device as claimed in claim 5 , comprising a plurality of switch transistors, wherein the drain of each of the plurality of switch transistors is input with the same transistor turn-on voltage.

9. The display device as claimed in claim 5 , wherein the gate drive area further comprises a gate drive circuit, and wherein the plurality of gate lines comprise portions located in the gate drive circuit.

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Zhang Yanping
• Yang Yuting
• Zhang Dayu
• Shao Xianjie

Classifications

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G5/18 Primary

  Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) · CPC title

• G09G2330/025

  Reduction of instantaneous peaks of current · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title