GOA circuit for LTPS-TFT

Patent metadata

Field	Value
Publication number	US-9875709-B2
Application number	US-201614917572-A
Country	US
Kind code	B2
Filing date	Jan 28, 2016
Priority date	Dec 22, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

The invention provides a GOA circuit for LTPS-TFT, using a resistor (R 1 ) and a tenth TFT (T 10 ) to replace the second capacitor in known technology, and change the diode-style connection of the ninth TFT (T 9 ) in known technology to connect one end of the resistor (R 1 ) to the constant high voltage (VGH) and the other to the gate of the ninth TFT (T 9 ) so that during the output end (G(n)) staying at low, the voltage of the second node (P(n)) follows the (M+1)-th clock signal (CK(M+1)) to switch between high and low, that is, following a fixed frequency to pull down the voltage of the second node (P(n)), prevents the second node from staying at high for long duration and prevents the sixth TFT (T 6 ) and the seventh TFT (T 7 ) from prolonged operation to cause threshold voltage shift and improve GOA circuit stability.

First claim

What is claimed is:

1. A gate driver on array (GOA) circuit for low temperature poly-silicon (LTPS) thin film transistor (TFT), which comprises: a plurality of cascade GOA units, each GOA unit comprising: an output control module, an output module, a bootstrap capacitor and a pull-down module;
for a positive integer n, other than the GOA unit in the first and the last stages, in the n-th GOA unit:
the output control module comprising: a first TFT, with a gate connected to an M-th clock signal, a source connected to an output end of a (n−1)-th GOA unit, and a drain connected to a third node; a third TFT, with a gate connected to an (M+2)-th clock signal, a drain connected to the third node, and a source connected to the output end of a (n+1)-th GOA unit; and a fifth TFT, with a gate connected to a constant high voltage, a source connected to the third node, and a drain connected to a first node;
the output module comprising: a second TFT, with a gate connected to the first node, a source connected to an (M+1)-th clock signal, and a drain connected to an output end;
the bootstrap capacitor having one end connected to the first node and the other end connected to the output end;
the pull-down module comprising: a fourth TFT, with a gate connected to an (M+3)-th clock signal, a drain connected to the output end, and a source connected to a constant low voltage; a sixth TFT, with a gate connected to a second node, a drain connected to the third node, and a source connected to the constant low voltage; a seventh TFT, with a gate connected to the second node, a drain connected to the output end, and a source connected to the constant low voltage; an eighth TFT, with a gate connected to the third node, a drain connected to the second node, and a source connected to the constant low voltage; a ninth TFT, with a gate connected to a fourth node, a source connected to the (M+1)-th clock signal, a and drain connected to the second node; a tenth TFT, with a gate connected to the third node, a drain connected to the fourth node, and a source connected to the constant low voltage; and a resistor, with one end connected to the constant high voltage and the other end connected to the fourth node.

2. The GOA circuit for LTPS-TFT as claimed in claim 1 , wherein during the output end staying at low, the voltage of the second node switches between high and low following the switching between high and low of the(M+1)-th clock signal.

3. The GOA circuit for LTPS-TFT as claimed in claim 1 , wherein in the first GOA unit, the first TFT has a source connected to a circuit start signal.

4. The GOA circuit for LTPS-TFT as claimed in claim 3 , wherein in the last GOA unit, the third TFT has a source connected to a circuit start signal.

5. The GOA circuit for LTPS-TFT as claimed in claim 1 , wherein the clock signals comprises four clock signals: the first clock signal, the second clock signal, the third clock signal and the fourth clock signal.

6. The GOA circuit for LTPS-TFT as claimed in claim 5 , wherein when the M-th clock signal is the third clock signal, the (M+2)-th clock signal and the (M+3)-th clock signal are the first clock signal and the second clock signal, respectively; when the M-th clock signal is the fourth clock signal, the (M+1)-th clock signal, the (M+2)-th clock signal and the (M+3)-th clock signal are the first clock signal, the second clock signal and the third clock signal, respectively.

7. The GOA circuit for LTPS-TFT as claimed in claim 4 , wherein during forward scanning, the first clock signal and the circuit start signal are provided first to the first TFT in the first GOA unit; during backward scanning, the first clock signal and the circuit start signal are provided first to the third TFT in the last GOA unit.

8. The GOA circuit for LTPS-TFT as claimed in claim 1 , wherein the TFTs are all of the N-type LTPS-TFTs.

9. A gate driver on array (GOA) circuit for low temperature poly-silicon (LTPS) thin film transistor (TFT), which comprises: a plurality of cascade GOA units, each GOA unit comprising: an output control module, an output module, a bootstrap capacitor and a pull-down module;
for a positive integer n, other than the GOA unit in the first and the last stages, in the n-th GOA unit:
the output control module comprising: a first TFT, with a gate connected to an M-th clock signal, a source connected to an output end of a (n−1)-th GOA unit, and a drain connected to a third node; a third TFT, with a gate connected to an (M+2)-th clock signal, a drain connected to the third node, and a source connected to the output end of a (n+1)-th GOA unit; and a fifth TFT, with a gate connected to a constant high voltage, a source connected to the third node, and a drain connected to a first node;
the output module comprising: a second TFT, with a gate connected to the first node, a source connected to an (M+1)-th clock signal, and a drain connected to an output end;
the bootstrap capacitor having one end connected to the first node and the other end connected to the output end;
the pull-down module comprising: a fourth TFT, with a gate connected to an (M+3)-th clock signal, a drain connected to the output end, and a source connected to a constant low voltage; a sixth TFT, with a gate connected to a second node, a drain connected to the third node, and a source connected to the constant low voltage; a seventh TFT, with a gate connected to the second node, a drain connected to the output end, and a source connected to the constant low voltage; an eighth TFT, with a gate connected to the third node, a drain connected to the second node, and a source connected to the constant low voltage; a ninth TFT, with a gate connected to a fourth node, a source connected to the (M+1)-th clock signal, and a drain connected to the second node; a tenth TFT, with a gate connected to the third node, a drain connected to the fourth node, and a source connected to the constant low voltage; and a resistor, with one end connected to the constant high voltage and the other end connected to the fourth node;
wherein in the first GOA unit, the first TFT has a source connected to a circuit start signal;
wherein the clock signals comprises four clock signals: the first clock signal, the second clock signal, the third clock signal and the fourth clock signal;
wherein the TFTs are all of the N-type LTPS-TFTs.

10. The GOA circuit for LTPS-TFT as claimed in claim 9 , wherein during the output end staying at low, the voltage of the second node switches between high and low following the switching between high and low of the(M+1)-th clock signal.

11. The GOA circuit for LTPS-TFT as claimed in claim 9 , wherein in the last GOA unit, the third TFT has a source connected to a circuit start signal.

12. The GOA circuit for LTPS-TFT as claimed in claim 9 , wherein when the M-th clock signal is the third clock signal, the (M+2)-th clock signal and the (M+3)-th clock signal are the first clock signal and the second clock signal, respectively; when the M-th clock signal is the fourth clock signal, the (M+1)-th clock signal, the (M+2)-th clock signal and the (M+3)-th clock signal are the first clock signal, the second clock signal and the third clock signal, respectively.

13. The GOA circuit for LTPS-TFT as claimed in claim 11 , wherein during forward scanning, the first clock signal and the circuit start signal are provided first to the first TFT in the first GOA unit; during backward scanning, the first clock signal and the circuit start signal are provided first to the third TFT in the last GOA unit.

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Li Yafeng

Classifications

• G09G2310/0283

  Arrangement of drivers for different directions of scanning · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• H01L27/1255

  Electricity · mapped topic

• G09G3/3677 Primary

  suitable for active matrices only · CPC title