High-speed latch circuits by selective use of large gate pitch

Patent metadata

Field	Value
Publication number	US-9875328-B2
Application number	US-201615235134-A
Country	US
Kind code	B2
Filing date	Aug 12, 2016
Priority date	Mar 10, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

An apparatus for storing data includes a latch circuit comprising a first set of transistors that propagate an input signal to an output signal and a second set of transistors that do not propagate the input signal of the latch circuit to the output signal wherein a gate pitch for the first set of transistors is substantially greater than a gate pitch for the second set of transistors. Also disclosed herein, a method for improving circuit performance includes receiving an electronic representation of a plurality of latching circuits associated with a design file and increasing transistor gate pitch for selected transistors of the plurality of latching circuits, wherein the selected transistors comprise transistors that propagate an input signal to an output signal. The method may also include fabricating a chip comprising the plurality of latching circuits. A computer program product corresponding to the method is also disclosed within.

First claim

What is claimed is:

1. A method, executed by a computer, for improving circuit performance, the method comprising:
receiving an electronic representation of a plurality of latching circuits associated with a design file; and
increasing a transistor gate pitch for selected transistors of the plurality of latching circuits, wherein the selected transistors comprise transistors that propagate an input signal of a latch to an output signal of the latch.

2. The method of claim 1 , wherein increasing the transistor gate pitch comprises at least doubling the transistor gate pitch.

3. The method of claim 1 , wherein the selected transistors comprise pass transistors.

4. The method of claim 1 , wherein the selected transistors comprise inverting transistors.

5. The method of claim 1 , wherein a latching circuit of the plurality of latching circuits comprises one or more transistors for test scan functionality.

6. The method of claim 1 , wherein the design file corresponds to a design library.

7. The method of claim 1 , wherein the design file corresponds to a chip design.

8. The method of claim 1 , further comprising updating the electronic representation of the plurality of latching circuits.

9. The method of claim 1 , further comprising fabricating a chip comprising the plurality of latching circuits.

10. A computer program product for improving circuit performance, the computer program product comprising:
one or more non-transitory computer-readable storage media and program instructions stored on the one or more non-transitory computer-readable storage media, the program instructions comprising instructions to:
receive an electronic representation of a plurality of latching circuits associated with a design file; and
increase a transistor gate pitch for selected transistors of the plurality of latching circuits, wherein the selected transistors comprise transistors that propagate an input signal of a latch to an output signal of the latch.

11. The computer program product of claim 10 , wherein the program instructions further comprise instructions to fabricate a chip comprising the plurality of latching circuits.

12. The computer program product of claim 10 , wherein the program instructions further comprise instructions to update the electronic representation of the plurality of latching circuits.

13. The computer program product of claim 10 , wherein the program instructions to increase the transistor gate pitch comprises instructions to at least double the transistor gate pitch.

14. The computer program product of claim 10 , wherein a latching circuit of the plurality of latching circuits comprises one or more transistors for test scan functionality.

15. The computer program product of claim 10 , wherein the design file corresponds to a chip design.

16. The computer program product of claim 10 , wherein the design file corresponds to a design library.

Assignees

• IBM

Inventors

• Chang Leland
• Montoye Robert K

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H03K3/356104 Primary

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title

• G06F17/5068

  Physics · mapped topic