System and method for providing a processing node with input/output functionality provided by an I/O complex switch

Patent metadata

Field	Value
Publication number	US-9875204-B2
Application number	US-201313897064-A
Country	US
Kind code	B2
Filing date	May 17, 2013
Priority date	May 18, 2012
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A processing node of a server rack includes a processor to generate processing node management requests and to process responses to the node management requests, and a communication module to receive the processing node management requests, to transmit over a communication link to a management controller of the server rack external to the processing node a processing node management request, to receive over the communication link from the management controller processing node management information, and to transmit the processing node management information to the processor.

First claim

What is claimed is:

1. A processing node of a server rack, the processing node comprising:
a processor to:
generate processing node management requests;
process responses to the node management requests;
generate remote direct memory access (RDMA) requests;
process responses to the RDMA requests;
generate real time clock (RTC) requests;
process responses to the RTC requests; and
generate debug information during booting, the debug information including information about checkpoints entered during booting and error messages received during booting; and

a communication module to;
receive the processing node management requests;
transmit over a communication link to a management controller of the server rack external to the processing node a processing node management request;
receive over the communication link from the management controller processing node management information;
transmit the processing node management information to the processor;
receive the RDMA requests;
transmit over the communication link to a RDMA block of the server rack external to the processing node a RDMA request for the remote direct memory access;
receive over the communication link from the RDMA block information associated with the RDMA request;
transmit the RDMA information to the processor;
receive the RTC requests;
transmit over the communication link to a RTC component of the server rack external to the processing node a RTC request;
receive over the communication link from the RTC component RTC information;
transmit the RTC information to the processor;
receive the debug information, to transmit the debug information over the communication link to a data logging component of the server rack external to the processing node;
receive alerts over the communication link from the data logging component of the server rack; and
transmit the alerts to the processor;

wherein the communication link includes a Peripheral Component Interconnect-Express (PCIe) link enumerated in a PCI configuration space of the processing node as a first PCIe link, the management controller is enumerated in the PCI configuration space as a first function of the first PCIe link, the RDMA block is enumerated in the PCI configuration space as a second function of the first PCIe link, the RTC component is enumerated in the PCI configuration space as a third function of the first PCIe link, and the data logging component is enumerated in the PCI configuration space as a fourth function of the first PCIe link.

2. The processing node of claim 1 , wherein:
the processor is further operable to generate network requests and to process responses to the network requests; and
the communication module is further operable to receive the network requests, to transmit over the communication link to a network interface controller of the server rack external to the processing node a network request, to receive over the communication link from the network interface controller network information associated with the network request, and to transmit the network information to the processor;
wherein the network interface controller is enumerated in the PCI configuration space as a fifth function of the first PCIe link.

3. The processing node of claim 1 , wherein:
the processor is further operable to generate storage requests and to process responses to the storage requests; and
the communication module is further operable to receive the storage requests, to transmit over the communication link to a storage interface block of the server rack external to the processing node a storage request, to receive over the communication link information associated with the storage request, and to transmit the information to the processor;
wherein the storage interface block is enumerated in the PCI configuration space as a fifth function of the first PCIe link.

4. The processing node of claim 1 , wherein:
the processor is further operable to generate basic input/output system (BIOS) requests, and to process responses to the BIOS requests; and
the communication module is further operable to receive the BIOS requests, to transmit over the communication link to a firmware component of the server rack external to the processing node the BIOS requests, to receive BIOS code over the communication link from the firmware component, and to transmit the BIOS code to the processing unit;
wherein the firmware component is enumerated in the PCI configuration space as a fifth function of the first PCIe link.

5. The processing node of claim 1 , wherein:
the communication module is further operable to receive periodic pulses over the communication link from a system clock component of the server rack external to the processing node; and
the processor further comprises a timing module to time communications over the communication link based upon the periodic pulses and to apply one or more multipliers to the periodic pulses to determine computer cycles of the processor;
wherein the system clock component is enumerated in the PCI configuration space as a fifth function of the first PCIe link.

6. The processing node of claim 1 , wherein:
the processing unit is further operable to generate video data; and
the communication module is further operable to receive the video data, to transmit the video data over a communication link to a video controller emulator of the server rack external to the processing node, to receive over the communication link from the video controller emulator of the server rack information about a status of a video display, and to transmit the information about the status of the video display to the processing unit, wherein the processing node does not contain a video adapter;
wherein the video controller emulator is enumerated in the PCI configuration space as a fifth function of the first PCIe link.

Assignees

• Dell Products Lp

Inventors

• Hormuth Robert W
• Winter Robert L
• Dube Shawn J
• Booth Bradley J
• Lin Geng
• Pike Jimmy

Classifications

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• H04L49/00

  Packet switching elements · CPC title

• H04L41/06

  Management of faults, events, alarms or notifications · CPC title

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F15/17331

  Distributed shared memory [DSM], e.g. remote direct memory access [RDMA] · CPC title