Data storage device with a memory die that includes an interleaver

Patent metadata

Field	Value
Publication number	US-9875156-B2
Application number	US-201514872473-A
Country	US
Kind code	B2
Filing date	Oct 1, 2015
Priority date	Oct 1, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A data storage device includes a set of latches, read/write circuitry, a memory, and an interleaver. The set of latches is configured to receive data. The read/write circuitry is coupled to the set of latches. The memory is coupled to the read/write circuitry. The interleaver is configured to interleave the data and to cause the read/write circuitry to program the interleaved data to the memory. The set of latches, the read/write circuitry, the memory, and the interleaver are integrated within a common die.

First claim

What is claimed is:

1. A data storage device comprising:
a set of latches configured to receive data;
read/write circuitry coupled to the set of latches;
a memory coupled to the read/write circuitry; and
an interleaver configured to interleave the data and to cause the read/write circuitry to program the interleaved data to a storage region of the memory,
wherein the read/write circuitry is configured to sense the storage region using a first sense technique associated with a first page and using a second sense technique associated with a second page to generate a deinterleaved representation of the data and to provide the deinterleaved representation of the data to the set of latches, and
wherein the set of latches, the read/write circuitry, the memory, and the interleaver are integrated within a common die.

2. The data storage device of claim 1 , wherein the read/write circuitry is configured to access the interleaved data from the set of latches and to program the interleaved data to a word line of the memory.

3. The data storage device of claim 2 , further comprising a counter, wherein the counter is configured to store a value indicating one or more values of the data during a read operation from the word line, the read operation including an on-the-fly (OTF) ramp sensing and deinterleaving process.

4. The data storage device of claim 1 , wherein the memory has a three-dimensional (3D) memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells having an active area above a silicon substrate, and further comprising circuitry associated with operation of the memory cells.

5. The data storage device of claim 1 , wherein the interleaver is further configured to interleave the data by shifting a bit of the data from the first page to the second page while maintaining a common bit position of the bit from the first page to the second page.

6. A method comprising:
in a data storage device that includes a controller coupled to a memory die, wherein the memory die includes a memory and a plurality of latches, performing by the memory die:
receiving data at the memory die from the controller, the data to be stored at the memory;
after receiving the data, performing an interleaving process associated with the data to generate interleaved data;
storing the interleaved data to a region of the memory;
sensing the region of the memory using a first read technique associated with a first page and using a second read technique associated with a second page to generate a deinterleaved representation of the data; and
providing the deinterleaved representation of the data to the plurality of latches.

7. The method of claim 6 , wherein the controller indicates that a first set of bits of the data and a second set of bits of the data are to be stored using the first page, and wherein the interleaving process includes causing the first set of bits to target the second page and causing the second set of bits to target a third page.

8. The method of claim 7 , wherein the first page is an upper page, wherein the second page is a middle page, and wherein the third page is a lower page.

9. The method of claim 7 , wherein the first set of bits and the second set of bits are included in an error correcting code (ECC) codeword.

10. The method of claim 7 , wherein the controller indicates that a third set of bits of the data is to be stored at the third page, and wherein the interleaving process further includes causing the third set of bits to target the first page.

11. The method of claim 7 , wherein the interleaving process includes a checkerboard interleaving process that enables the memory die to avoid horizontal shifting of the data.

12. The method of claim 6 , wherein the interleaving process is performed using logical operations at the plurality of latches.

13. The method of claim 6 , wherein the interleaving process is an on-the-fly (OTF) interleaving process that includes performing a verification process that uses a first group of verify levels for a first group of storage elements of the memory, a second group of verify levels for a second group of storage elements of the memory, and a third group of verify levels for a third group of storage elements of the memory.

14. The method of claim 13 , wherein the verification process is performed using a ramp sensing technique.

15. The method of claim 14 , wherein the ramp sensing technique includes accessing counter bits stored by a counter.

16. The method of claim 15 , wherein a different permuted version of the counter bits is accessed for a first group of storage elements of the memory and a second group of storage elements of the memory.

17. The method of claim 6 , wherein the interleaving process is performed using an on-die copy operation from a single-level cell (SLC) partition of the memory to a tri-level-cell (TLC) partition of the memory.

18. The method of claim 17 , further comprising:
prior to interleaving the data:
programming the data to the SLC partition; and
reading the data from the SLC partition, wherein the data is interleaved after reading the data from the SLC partition; and

after interleaving the data to generate the interleaved data, programming the interleaved data to a TLC word line of the TLC partition so that different portions of the data are stored using different logical pages of the TLC word line.

19. The method of claim 6 , further comprising:
receiving a request for read access from the controller;
wherein sensing the region of the memory includes performing, in response to the request, a sensing process to generate a representation of a first interleaved page, a representation of a second interleaved page, and a representation of a third interleaved page; and
wherein providing the deinterleaved representation of the data to the plurality of latches includes providing the representation of the first interleaved page to a first latch of the plurality of latches, the representation of the second interleaved page to a second latch of the plurality of latches, and the representation of the third interleaved page to a third latch of the plurality of latches.

20. The method of claim 19 , further comprising performing a change-columns deinterleaving process, wherein the change-columns deinterleaving process includes:
while the first latch stores a representation of a first portion of the first interleaved page, moving a representation of a second portion of the second interleaved page from the second latch to the first latch; and
moving a representation of a third portion of the third interleaved page from the third latch to the second latch.

21. The method of claim 6 , further comprising receiving the data from the controller at the plurality of latches, wherein the interleaving process is performed after receiving the data at the plurality of latches.

22. A device comprising:
means for storing interleaved data;
means for performing an on-the-fly (OTF) deinterleaving and ramp sensing process using a first sensing technique associated with a first page and using a second sensing technique associated with a second page to generate a representation of the interleaved data, wherein the representation corresponds to deinterleaved data; and
means for receiving the representation from the means for performing the OTF deinterleaving and ramp sensing process and for storing the representation,
wherein the means for storing the interleaved data, the means

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Sharon Eran
• Navon Ariel
• Chu Alexander Tsang-Nam
• Tsai Wanfang
• Alrod Idan

Classifications

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• H03M13/2792

  Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G06F11/1072 Primary

  in multilevel memories · CPC title