Apparatus, system, and method for persistent user-level thread

Patent metadata

Field	Value
Publication number	US-9875102-B2
Application number	US-201615386615-A
Country	US
Kind code	B2
Filing date	Dec 21, 2016
Priority date	Sep 30, 2005
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.

First claim

What is claimed is:

1. An apparatus comprising:
a first plurality of cores to execute an operating system; and
a second plurality of cores, wherein the second plurality of cores are to not be visible to the operating system, wherein at least one of the first plurality of cores is to execute an application that is to schedule work, independently of the operating system, to at least one of the second plurality of cores, the at least one of the first plurality of cores and the at least one of the second plurality of cores to execute in a shared virtual address space, and wherein in response to a page fault encountered by the at least one of the second plurality of cores, one or more of the first plurality of cores are to execute the operating system to handle the page fault.

2. The apparatus of claim 1 , wherein the at least one core of the first plurality of cores comprises at least one operating system-visible sequencer to execute instructions scheduled by the operating system and the at least one core of the second plurality of cores comprises at least one operating system-sequestered sequencer for which the operating system does not schedule instructions.

3. The apparatus of claim 2 , wherein the at least one operating system-visible sequencer is to create a persistent user-level thread of the application to run on the at least one operating system-sequestered sequencer.

4. The apparatus of claim 3 , wherein the persistent user-level thread is to continue execution, irrespective of context switch activities of an operating system-scheduled thread of the application executed on the at least one operating system-visible sequencer, and the processor is to suspend execution of the persistent user-level thread in response to the page fault, and communicate to a second operating system-visible sequencer a control transfer instruction for execution at a privileged level.

5. The apparatus of claim 4 , further comprising a sequencer manager to cause a service thread to execute on the at least one operating system-visible sequencer to handle the page fault for the suspended persistent user-level thread, wherein the sequencer manager is to:
cause the service thread to pick up a state of the persistent user-level thread;
provide a proxy execution to the persistent user-level thread; and
return a post execution state to the persistent user-level thread to enable the persistent user-level thread to resume running from the post execution state.

6. The apparatus of claim 1 , further comprising a digital signal processor (DSP).

7. The apparatus of claim 1 , wherein the at least one core of the second plurality of cores is to process a subset of instructions to be processed by the at least one core of the first plurality of cores.

8. The apparatus of claim 1 , wherein the apparatus comprises a multi-threaded processor.

9. The apparatus of claim 1 , wherein the apparatus comprises a chip multiprocessor.

10. The apparatus of claim 1 , wherein the at least one core of the first plurality of cores comprises a complex instruction set computer processor and the at least one core of the second plurality of cores comprises a reduced instruction set computer processor.

11. An apparatus comprising:
a first plurality of sequencers to execute an operating system, the first plurality of sequencers comprising a first plurality of hardware cores;
a second plurality of sequencers, wherein the second plurality of sequencers are to not be visible to the operating system, the second plurality of sequencers comprising a second plurality of hardware cores; and
a sequencer manager to virtualize the first plurality of sequencers and the second plurality of sequencers;
wherein at least one sequencer of the first plurality of sequencers is to execute an application that is to schedule work, independently of the operating system, to at least one sequencer of the second plurality of sequencers, the at least one sequencer of the first plurality of sequencers and the at least one sequencer of the second plurality of sequencers to execute in a shared virtual address space, and wherein in response to a page fault encountered by the at least one sequencer of the second plurality of sequencers, one or more of the first plurality of sequencers are to execute the operating system to handle the page fault.

12. The apparatus of claim 11 , wherein the sequencer manager comprises a driver.

13. The apparatus of claim 11 , wherein the sequencer manager is to control access to the first plurality of sequencers and the second plurality of sequencers.

14. The apparatus of claim 11 , wherein the sequencer manager is to provide execution resources to the application via access to at least some of the first plurality of sequencers and the second plurality of sequencers.

15. The apparatus of claim 11 , wherein the sequencer manager is to assign one or more threads of the work to the at least one sequencer of the second plurality of sequencers in one or more time slots.

16. The apparatus of claim 11 , wherein the first plurality of sequencers are asymmetric to the second plurality of sequencers.

17. A method comprising:
executing, on at least one core of a first plurality of cores of a multicore processor, an application;
scheduling a first thread of the application, independently of an operating system, to at least one core of a second plurality of cores of the multicore processor, wherein the second plurality of cores are not visible to the operating system;
executing the application on the at least one core of the first plurality of cores and the at least one core of the second plurality of cores in a shared virtual address space; and
in response to a page fault encountered by the at least one core of the second plurality of cores, executing the operating system on one or more cores of the first plurality of cores to handle the page fault.

18. The method of claim 17 , further comprising virtualizing, using a sequencer manager of the multicore processor, at least some of the first plurality of cores and at least some of the second plurality of cores.

19. At least one non-transitory computer readable storage medium comprising instructions that when executed enable a system to:
execute, on at least one core of a first plurality of cores of a multicore processor, an application;
schedule a first thread of the application, independently of an operating system, to at least one core of a second plurality of cores of the multicore processor, wherein the second plurality of cores are not visible to the operating system;
execute the application on the at least one core of the first plurality of cores and the at least one core of the second plurality of cores in a shared virtual address space; and
in response to a page fault encountered by the at least one core of the second plurality of cores, handle the page fault on one or more cores of the first plurality of cores.

20. The at least one non-transitory computer readable medium of claim 19 , further comprising instructions that when executed enable the system to virtualize, using a sequencer manager of the multicore processor, at least some of the first plurality of cores and at least some of the second plurality of cores.

Assignees

• Intel Corp

Inventors

• Chinya Gautham
• Wang Hong
• Sethi Prashant
• Kaushik Shivnandan
• Bigbee Bryant
• Shen John
• Hankins Richard
• Zou Xiang
• Patel Baiju V
• Brandt Jason W
• Aggarwal Anil
• Reid John L

Classifications

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/461

  Saving or restoring of program or task context · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F9/3009 Primary

  Thread control instructions · CPC title

• G06F9/3885

  using a plurality of independent parallel functional units · CPC title