Memory system and method of generating a seed value

Patent metadata

Field	Value
Publication number	US-9875085-B2
Application number	US-201514811481-A
Country	US
Kind code	B2
Filing date	Jul 28, 2015
Priority date	Jul 28, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A memory system and method are provided for generating a seed value. In one embodiment, a memory system identifies a random defect in a memory die and, in accordance with the identified random defect in the memory die, generates a seed value, wherein with the generated seed value a random number can be generated. Other embodiments are provided, which can be used alone or in combination with one another.

First claim

What is claimed is:

1. A method for generating a seed value, the method comprising:
performing the following in a memory system having a plurality of memory dies:
identifying random defects in the plurality of memory dies; and
in accordance with the identified random defects, generating a seed value by:
generating a string listing the identified random defects and which memory dies they are located in;
generating a random seed vector by inputting the string into a random function; and
generating a random seed value from the random seed vector,

wherein a random number can be generated with the random seed value.

2. The method of claim 1 , wherein:
the plurality of memory dies are configured to store information about the random defects in the plurality of memory dies; and
the random defects in the plurality of memory dies are identified by reading the information from the plurality of memory dies.

3. The method of claim 1 further comprising generating the random number based on the random seed value.

4. The method of claim 3 , wherein the random number is generated by a hardware random number generator in a controller in the memory system.

5. The method of claim 4 , wherein the hardware random number generator comprises:
a transducer to convert a physical phenomenon to an electrical signal;
an amplifier to increase amplitude of the electrical signal; and
an analog-to-digital converter to convert an amplified digital signal to a digital number.

6. The method of claim 3 , wherein the random number is generated by a controller in the memory system executing computer-readable program code.

7. The method of claim 6 , wherein the random number is generated using a software routine that uses a clock of the controller as an input.

8. The method of claim 1 further comprising:
identifying an additional random defect in the plurality of memory dies; and
generating a new seed value based on the identified additional random defect.

9. The method of claim 1 , wherein the random defects are identified by one or more of the following: a bad block list, a bad bit location, a partial bad block list, a partial good block list, a grown bad block list, and a list of defective wordlines.

10. The method of claim 1 , wherein at least one of the plurality of memory dies is a three-dimensional memory.

11. The method of claim 1 , wherein the memory system is embedded in a host.

12. The method of claim 1 , wherein the memory system is removably connected to a host.

13. A memory system comprising:
a plurality of memory dies; and
a controller in communication with the plurality of memory dies, wherein the controller is configured to:
identify random inherent characteristics in the plurality of memory dies; and
generate a seed value for generation of a random number based on the identified random inherent characteristics, wherein the controller is configured to generate the seed value by:
generating a string listing the identified random inherent characteristics and which memory dies they are located in;
generating a random seed vector by inputting the string into a random function; and
generating a random seed value from the random seed vector.

14. The memory system of claim 13 , wherein:
the plurality of memory dies are configured to store information about the random inherent characteristics in the plurality of memory dies; and
the controller is configured to identify the random inherent characteristics in the plurality of memory dies by reading the information from the plurality of memory dies.

15. The memory system of claim 13 , wherein the controller is further configured to generate a random number based on the seed value.

16. The memory system of claim 15 , wherein the controller is configured to generate the random number using a hardware random number generator in the controller.

17. The memory system of claim 15 , wherein the controller is configured to generate the random number by executing computer-readable program code.

18. The memory system of claim 13 , wherein the controller is further configured to:
identify an additional random inherent characteristic in the plurality of memory dies; and
generate a new seed value based the identified additional random inherent characteristic.

19. The memory system of claim 13 , wherein the random inherent characteristics are identified by one or more of the following: a bad block list, a bad bit location, a partial bad block list, a partial good block list, a grown bad block list, a list of defective wordlines, a read scrub queue, memory trim parameters, and a state of a random number generator.

20. The memory system of claim 13 , wherein at least one of the plurality of memory dies is a three-dimensional memory.

21. The memory system of claim 13 , wherein the memory system is embedded in a host.

22. The memory system of claim 13 , wherein the memory system is removably connected to a host.

23. A memory system comprising:
a plurality of memory dies;
means for identifying random defects in the plurality of memory dies;
means for generating a string listing the identified random defects and which memory dies they are located in;
means for generating a random seed vector by inputting the string into a random function; and
means for generating a random seed value from the random seed vector, wherein a random number can be generated with the random seed value.

24. The memory system of claim 23 further comprising means for generating the random number based on the random seed value.

25. The memory system of claim 23 , wherein the random defects are identified by one or more of the following: a bad block list, a bad bit location, a partial bad block list, a partial good block list, a grown bad block list, and a list of defective wordlines.

26. The memory system of claim 23 , wherein at least one of the plurality of memory dies is a three-dimensional memory.

27. The memory system of claim 23 , wherein the memory system is embedded in a host.

28. The memory system of claim 23 , wherein the memory system is removably connected to a host.

29. The memory system of claim 23 further comprising means for generating a random seed over a life time of the memory system based on a random string comprising an initial defect in the memory system, a new added random defect, and a random parameter.

30. The memory system of claim 29 , wherein the added random defect comprises one or more of the following: a grown bad block, a grown partial bad block, and a grown partial good block.

31. The memory system of claim 29 , wherein the random parameter comprises one or more of the following: a read scrub queue entry, a linear-feedback shift register (LFSR) state, and a trimming parameter.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Mukhopadhyay Rishi
• Manohar Abhijeet
• Neermarga Rajesh

Classifications

• G06F7/588 Primary

  Random number generators, i.e. based on natural stochastic processes · CPC title

• G06F7/584

  using finite field arithmetic, e.g. using a linear feedback shift register · CPC title