Storage device including nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-9875038-B2
Application number	US-201615083524-A
Country	US
Kind code	B2
Filing date	Mar 29, 2016
Priority date	Jun 24, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A storage device including a nonvolatile memory device is provided. The storage device may include: a nonvolatile memory device; and a controller configured to control a read operation of the nonvolatile memory device according to a read request from an external host device. The controller is configured to read map data including a segment, and to store different types of map data in an internal random access memory (RAM) based on determining whether the segment corresponds to sequential data.

First claim

What is claimed is:

1. A storage device comprising:
a nonvolatile memory device; and
a controller configured to control a read operation of the nonvolatile memory device according to a read request from an external host device,
wherein the controller is configured to read map data including a segment, store different types of map data in an internal random access memory (RAM) based on determining whether the segment corresponds to sequential data, and generate cache map data indicating that the segment corresponds to the sequential data to store the cache map data, if the segment corresponds to the sequential data.

2. The storage device of claim 1 , wherein the controller is configured to receive the read request based on logical addresses, convert the logical addresses into physical addresses of the nonvolatile memory device, and control the read operation based on the converted physical addresses.

3. The storage device of claim 2 , wherein the controller is configured to read the map data including the segment corresponding to the logical addresses.

4. The storage device of claim 1 , wherein the controller is configured to store partial map data, associating logical addresses with physical addresses of the segment, among the map data, if the segment does not correspond to the sequential data.

5. The storage device of claim 4 , wherein the cache map data comprises information about a start physical address of the segment and a start logical address related to the start physical address.

6. The storage device of claim 4 , wherein the controller is configured to convert, if cache map data corresponding to the logical addresses is stored in the internal RAM, the logical addresses into the physical addresses using the cache map data stored in the internal RAM.

7. The storage device of claim 6 , wherein the controller is configured to determine whether cache map data corresponding to the logical addresses is stored in the internal RAM based on a set associative cache.

8. The storage device of claim 4 , wherein the controller is configured to store, in the internal RAM, cache map data indicating that a first segment corresponding to the logical addresses corresponds to sequential data, if the first segment corresponds to the sequential data and to store cache map data indicating that a second segment which is smaller than the first segment and corresponds to the logical addresses corresponds to sequential data, if the first segment does not correspond to sequential data and the second segment corresponds to sequential data.

9. The storage device of claim 8 , wherein a size of the first segment and a size of the second segment are determined according to operating characteristics of the controller and the nonvolatile memory device.

10. The storage device of claim 8 , wherein a size of the first segment and a size of the second segment are determined according to operating characteristics of the controller and the external host device.

11. The storage device of claim 4 , wherein the segment comprises a plurality of entries, and
wherein each of the plurality of entries comprises conversion information between a logical address and a physical address.

12. The storage device of claim 11 , wherein the cache map data comprises a start entry of the segment, and
wherein the partial map data comprises entries corresponding to the logical addresses.

13. The storage device of claim 12 , wherein the start entry further comprises a cache tag indicating that the segment corresponds to sequential data.

14. The storage device of claim 1 , wherein the nonvolatile memory device comprises a plurality of memory blocks,
wherein each of the plurality of memory blocks comprises a plurality of cell strings arranged on a substrate,
wherein each of the plurality of cell strings comprises at least one selection transistor and a plurality of memory cells stacked on the substrate in a direction perpendicular to the substrate, and
wherein each of the at least one selection transistor and the plurality of memory cells comprises a charge trap layer.

15. A storage device comprising:
a nonvolatile memory device; and
a controller configured to control a write operation of the nonvolatile memory device according to a write request from an external host device,
wherein the controller is configured to generate map data, to store the generated map data as different types of map data in an internal random access memory (RAM) based on determining whether write data is sequential, to write the generated map data and the write data corresponding to the write request in the nonvolatile memory device, and to generate cache map data indicating that the write data is sequential to store the cache map data, if a range in which the logical addresses of the write data are continuous is greater than or equal to a segment corresponding to the cache map data.

16. The storage device of claim 15 , wherein the controller is configured to receive the write request based on logical addresses, convert the logical addresses into physical addresses of the nonvolatile memory device, and control the write operation based on the converted physical addresses.

17. The storage device of claim 16 , wherein the controller is configured to generate the map data including conversion information between the logical addresses and the physical addresses.

18. The storage device of claim 15 , wherein the controller is configured to store map data associating logical addresses with physical addresses of the write data as partial map data, if a range in which the logical addresses of the write data are continuous is smaller than the segment.

19. A method of operating a storage device which includes a nonvolatile memory device and a controller configured to control the nonvolatile memory device, the method comprising:
receiving a write request from an external host device;
generating map data for associating logical addresses corresponding to the write request with physical addresses of the nonvolatile memory device;
generating cache map data corresponding to at least one segment if a range in which the logical addresses are continuous is greater than or equal to the at least one segment; and
storing the cache map data in an internal random access memory (RAM) of the controller, if the range in which the logical addresses are continuous is greater than or equal to the at least one segment.

20. The method of claim 19 , further comprising:
storing the generated map data as partial map data in the internal RAM of the controller, if a range in which the logical addresses are continuous is smaller than the at least one segment.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jang Dae-Hoon
• Kim Bomi
• Yoon Songho

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/0613 Primary

  in relation to throughput · CPC title

• G06F2212/7207

  management of metadata or control data · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title