Method and structure for integrating photonics with CMOs

Patent metadata

Field	Value
Publication number	US-9874693-B2
Application number	US-201514735622-A
Country	US
Kind code	B2
Filing date	Jun 10, 2015
Priority date	Jun 10, 2015
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

A semiconductor structure can include an active device FET region having a FET and a photonics region having a photonic device including a waveguide. A semiconductor structure can include an active device FET region having a FET and a trench isolation region having a photonic device that includes a waveguide. A method can include forming a FET at an active device FET region of a semiconductor structure. A method can include forming a photonic device at a trench isolation region of a semiconductor structure.

First claim

What is claimed is:

1. A method of fabricating a photonic structure comprising:
fabricating a gate structure for a field effect transistor (FET) at a FET region of a semiconductor structure that includes a FET region and a trench isolation region;
forming one or more dielectric layer that extends over the gate structure at the FET region and over a trench dielectric layer of the trench isolation region;
removing a section of the one or more dielectric layer at the trench isolation region;
forming a waveguiding material layer that extends over the trench dielectric layer of the trench isolation region; and
patterning the waveguiding material layer to provide a photonic device having a waveguide defined by the waveguiding material layer at the trench isolation region.

2. The method of claim 1 , wherein the forming includes forming the waveguiding material layer so that the waveguiding material layer extends over the gate structure.

3. The method of claim 1 , wherein the gate structure is a non-sacrificial gate structure.

4. The method of claim 1 , wherein the gate structure is a sacrificial gate structure.

5. The method of claim 1 , wherein the forming includes forming the waveguiding material layer that extends over the trench dielectric layer of the trench isolation region and over a substrate of the trench isolation region, wherein the fabricating a gate structure includes forming a semiconductor material layer that extends over a substrate of the FET region and over the trench dielectric layer and a substrate of the trench isolation region, wherein the method includes patterning the semiconductor material layer at the FET region to form the gate structure, and patterning the semiconductor material layer to form a photonic device having a waveguide defined by the semiconductor material layer at the trench isolation region.

6. The method of claim 5 , wherein the photonic device having a waveguide defined by the semiconductor material has a thickness less than a thickness of the waveguide defined by the waveguiding material layer.

7. The method of claim 5 , wherein the photonic device is a photonic device selected from the group consisting of a photodetector, a grating coupler, a modulator and a waveguide.

8. The method of claim 1 , wherein the method includes patterning the waveguiding material layer at a first section of the trench isolation region to provide a photodetector having a waveguide defined by the waveguiding material layer, patterning the waveguiding material layer at a second section of the trench isolation region to provide a grating coupler having a waveguide defined by the waveguiding material layer, and patterning the waveguiding material layer at a third section of the trench isolation region to provide a modulator having a waveguide defined by the waveguiding material layer.

9. The method of claim 1 , wherein the method includes performing ion implantation of a substrate to form halos and extensions within the FET region prior to the forming of the waveguiding material layer.

10. The method of claim 1 , wherein the method includes forming in a substrate of the semiconductor structure a deep trench and a shallow trench.

11. The method of claim 1 , wherein the gate structure is defined by a semiconductor material layer. and wherein one or more of the semiconductor material layer or the waveguiding material layer is subject to ion implantation to modify a silicon crystal structure of the one or more of the semiconductor material layer or the waveguiding material layer.

12. The method of claim 1 , wherein the gate structure is defined by a semiconductor material layer. and wherein one or more of the semiconductor material layer or the waveguiding material layer is subject to annealing for modification of a grain structure of the one or more of the semiconductor material layer or the waveguiding material layer.

13. The method of claim 1 , wherein the forming one or more dielectric layer includes using a first layer of a first dielectric material and a second layer of a second dielectric material, wherein the method includes forming the second layer over the first layer, and wherein the method include patterning the first layer to define a spacer for a FET having the gate structure.

14. A semiconductor structure comprising:
a FET region and a trench isolation region;
a first section of a semiconductor material layer formed over a substrate within the FET region; and
a second section of the semiconductor material layer discontinuous with the first section of a semiconductor material layer, the second section formed over a trench dielectric layer of the trench isolation region, wherein the semiconductor structure includes (a) a first spacer adjacent to the first section of a semiconductor material layer, (b) a second spacer for the first section of a semiconductor material layer adjacent to the feature (a), (c) a first spacer adjacent to the second section of the semiconductor material layer, (d) a second spacer for the second section of the semiconductor material layer adjacent to the feature (c), wherein the features (a) and (c) are of a common material, and wherein the features (b) and (d) are of a common material.

15. The semiconductor structure of claim 14 , wherein the trench isolation region is a deep trench isolation region.

16. The semiconductor structure of claim 14 , wherein the semiconductor structure includes one or more of a source-drain halos or a source-drain extension formed within the FET region.

17. The semiconductor structure of claim 14 , wherein the semiconductor structure includes (a) a first spacer adjacent to the first section of a semiconductor material layer and (b) a first spacer adjacent to the second section of the semiconductor material layer, wherein the features (a) and (b) are of a common material.

18. The semiconductor structure of claim 14 , having a first dielectric layer formed over the substrate, the first dielectric layer extending within the FET region and extending within the trench isolation region.

19. The semiconductor structure of claim 14 , having a first dielectric layer formed over the substrate, and a second dielectric layer formed over the first dielectric layer, the first dielectric layer and the second dielectric layer extending within the FET region and extending within the trench isolation region, the first dielectric layer being formed of a first dielectric material, the second dielectric layer being formed of a second dielectric material.

20. A semiconductor structure comprising:
a FET region and a trench isolation region;
one or more field effect transistor gate structure formed over a substrate within the FET region; and
one or more photonic device formed over a trench dielectric layer of the trench isolation region, wherein the trench dielectric layer of the trench isolation region fills a trench of the trench isolation region, and wherein the trench is formed in the substrate.

21. The semiconductor structure of claim 20 , wherein the one or more photonic device is a waveguide.

22. The semiconductor structure of claim 20 , wherein the one or more field effect transistor gate structure is a polysilicon gate structure.

23. The semiconductor structure of claim 20 , wherein the one or more photonic device includes a first waveguide of a first height and a second waveguide of a second height.

24. The semiconductor structure of claim 20 , wherein the FET region includes a f

Assignees

• Baiocco Christopher
• Coolbaugh Douglas
• Leake Gerald
• Univ New York State Res Found

Inventors

• Baiocco Christopher
• Coolbaugh Douglas
• Leake Gerald

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H01L21/26506

  Electricity · mapped topic